`timescale 1ns/1ps

module clock_gen (input enable, output reg clk);

parameter FREQ = 1000;  // in HZ
parameter PHASE = 0;    // in degrees
parameter DUTY = 50;    // in percentage 

real clk_pd	= 1.0/FREQ * 1000000; 	// convert to ms
real clk_on	= DUTY/100.0 * clk_pd;
real clk_off	= (100.0 - DUTY)/100.0 * clk_pd;
real quarter	= clk_pd/4;
real start_dly	= quarter * PHASE/90;

reg start_clk;

initial begin
end

// Initialize variables to zero
initial begin
	clk <= 0;
	start_clk <= 0;
end

// When clock is enabled, delay driving the clock to one in order
// to achieve the phase effect. start_dly is configured to the 
// correct delay for the configured phase. When enable is 0,
// allow enough time to complete the current clock period
always @ (posedge enable or negedge enable) begin
	if (enable) begin
		#(start_dly) start_clk = 1;
	end else begin
		#(start_dly) start_clk = 0;
	end      
end

// Achieve duty cycle by a skewed clock on/off time and let this
// run as long as the clocks are turned on.
always @(posedge start_clk) begin
	if (start_clk) begin
		clk = 1;

		while (start_clk) begin
			#(clk_on)  clk = 0;
			#(clk_off) clk = 1;
		end

		clk = 0;
	end
end 
endmodule


module processor ( input clock, input reset , output reg [19:0] external_address_bus, inout [15:0] external_data_bus,output reg read, output reg write);
/* State */
reg [1:0] state;
reg start=0;
reg instruction_finished;

/* Registers */
reg [19:0] ProgCount;


/* RESET LOGIC */
always @(negedge reset) begin
	if (reset==0) begin
		@(posedge clock);
		state=0;
		ProgCount=0;//TODO: Reset Vector
		#10
		start=1;
	end
end

/* CLOCK LOGIC */
always @(posedge clock) begin
	if(instruction_finished) begin 
		state =0;
	end else begin
		if (clock && start==1) begin
			state=state+1;
		end
	end
end

always @(state) begin
	if (state==2) begin
		instruction_finished=1;
	end else begin
		instruction_finished=0;
	end
end

/* Processor stages */
always @(state) begin
	if (state==0) begin
		external_address_bus <= ProgCount;
		read <= 0;
		write <= 1;
	end
end

endmodule