/* processor.v - implementation of most functions of the 9086 processor

   This file is part of the 9086 project.

   Copyright (c) 2023 Efthymios Kritikos

   This program is free software: you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation, either version 3 of the License, or
   (at your option) any later version.

   This program is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   GNU General Public License for more details.

   You should have received a copy of the GNU General Public License
   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */

`include "proc_state_def.v"
`include "alu_header.v"
`include "config.v"
`include "ucode_header.v"

//HALT: active high
//ERROR: active high
//IOMEM: 1=IO  0=MEM
//write: active low
//read: active low
//reset: active low

module processor ( input clock, input reset, output reg [19:0] external_address_bus, inout [15:0] external_data_bus,output reg read, output reg write,output reg BHE,output reg IOMEM, output reg HALT,output reg ERROR);

/*if we don't read, output the register to have the bus stable by the write falling edge*/
reg [15:0] data_bus_output_register;
assign external_data_bus=read?data_bus_output_register:16'hz;

/*** Global Definitions ***/

reg [`PROC_STATE_BITS-1:0] state;

/*############ Decoder ########################################################## */
wire Wbit, Sbit, opcode_size;
wire [`PROC_STATE_BITS-1:0] next_state;
wire [2:0]RM;
wire [15:0]DE_PARAM1;// Input param1 form decoder to alu
wire [15:0]DE_PARAM2;
wire DE_ERROR,DE_HALT;
wire [3:0]DE_reg_read_port1_addr,DE_reg_write_addr,DE_reg_read_port2_addr;
wire [11:0]DE_REGISTER_CONTROL;
wire [2:0]INSTRUCTION_INFO;
wire [1:0]DECODER_SIGNALS;
wire [`UCODE_ADDR_BITS-1:0] ucode_seq_addr_entry;

reg SIMPLE_MICRO; /* output simple decodings (=0) or microcode data (=1) */
wire [2:0] DE_instruction_size;
reg instruction_size_init;
wire [2:0] instruction_size;
assign instruction_size = instruction_size_init ? 3'b010 : DE_instruction_size;
wire memio_address_select;
wire MEM_OR_IO;

decoder decoder(
	.CIR(CIR),
	.FLAGS(FLAGS),
	.INSTRUCTION_INFO(INSTRUCTION_INFO),
	.DECODER_SIGNALS(DECODER_SIGNALS),
	.next_state(next_state),
	.IN_MOD(IN_MOD),
	.RM(RM),
	.PARAM1(DE_PARAM1),
	.PARAM2(DE_PARAM2),
	.in_alu1_sel1(in_alu1_sel1),
	.in_alu1_sel2(in_alu1_sel2),
	.OUT_MOD(OUT_MOD),
	.REGISTER_FILE_CONTROL(DE_REGISTER_CONTROL),
	.ALU_1OP(ALU_1OP),
	.seq_addr_entry(ucode_seq_addr_entry),
	.SIMPLE_MICRO(SIMPLE_MICRO),
	.seq_addr_input(ucode_seq_addr),
	.instruction_size(DE_instruction_size),
	.memio_address_select(memio_address_select),
	.MEM_OR_IO(MEM_OR_IO)
);

assign Wbit=INSTRUCTION_INFO[2:2];
assign Sbit=INSTRUCTION_INFO[1:1];
assign opcode_size=INSTRUCTION_INFO[0:0];

assign DE_reg_write_addr=DE_REGISTER_CONTROL[11:8];
assign DE_reg_read_port1_addr=DE_REGISTER_CONTROL[7:4];
assign DE_reg_read_port2_addr=DE_REGISTER_CONTROL[3:0];

assign DE_HALT=DECODER_SIGNALS[0:0];
assign DE_ERROR=DECODER_SIGNALS[1:1];

reg [`UCODE_ADDR_BITS-1:0] ucode_seq_addr;

/*############ REGISTERS ########################################################## */

reg [15:0] CIR;
reg [15:0] PARAM1;
reg [15:0] PARAM2;

// verilator lint_off UNDRIVEN
reg [15:0] FLAGS;
// verilator lint_on UNDRIVEN

//Architectural Register file
reg [3:0] reg_write_addr;
wire [15:0] reg_write_data;
reg reg_write_we;
reg [3:0] reg_read_port1_addr;
reg [15:0] reg_read_port1_data;
reg [3:0] reg_read_port2_addr;
reg [15:0] reg_read_port2_data;
reg [1:0] reg_write_in_sel;
mux4 #(.WIDTH(16)) REG_FILE_WRITE_IN_MUX(
	ALU_1O,
	16'hz,
	16'hz,
	16'hz,
	reg_write_in_sel,
	reg_write_data);
register_file register_file(
	.write_port1_addr(reg_write_addr),
	.write_port1_data(reg_write_data),
	.write_port1_we(reg_write_we),
	.read_port1_addr(reg_read_port1_addr),
	.read_port1_data(reg_read_port1_data),
	.read_port2_addr(reg_read_port2_addr),
	.read_port2_data(reg_read_port2_data)
);

reg [15:0] ProgCount;

/*############ ALU / Execution units ########################################################## */
//  ALU 1
reg [1:0] in_alu1_sel1;
reg [1:0] in_alu1_sel2;
/* OUT_MOD : { EXTRA_FUNCTIONS_BIT[0:0], MOD_OR_EXTRA_FUNCTION[1:0] } */
reg [2:0] IN_MOD;
reg [2:0] OUT_MOD;

mux4 #(.WIDTH(16)) MUX16_1A(
/*0*/	PARAM1,
/*1*/	reg_read_port1_data,
/*2*/	ProgCount[15:0],
/*3*/	16'd0, /*0 Constant*/
	in_alu1_sel1,
	ALU_1A);

mux4 #(.WIDTH(16)) MUX16_1B(
/*0*/	PARAM2,
/*1*/	reg_read_port2_data,
/*2*/	ProgCount[15:0],
/*3*/	16'd0, /*0 Constant*/
	in_alu1_sel2,
	ALU_1B);

wire [15:0] ALU_1A;
wire [15:0] ALU_1B;
wire [15:0] ALU_1O;
reg [`ALU_OP_BITS-1:0]ALU_1OP;
wire [7:0] ALU_1FLAGS;
ALU ALU1(
	.A(ALU_1A),
	.B(ALU_1B),
	.OUT(ALU_1O),
	.op(ALU_1OP),
	.FLAGS(ALU_1FLAGS),
	.Wbit(Wbit)
);

/*############ Processor state machine ########################################################## */

/*** RESET LOGIC ***/
/* verilator lint_off MULTIDRIVEN */
always @(negedge reset) begin
	state <= `PROC_HALT_STATE; //TODO: race condition ??
end
always @(posedge reset) begin
	state <= `PROC_RESET;
end
/* verilator lint_on MULTIDRIVEN */

/*** Processor stages ***/
`define invalid_instruction state <= `PROC_IF_STATE_ENTRY;ERROR <= 1;

always @(posedge clock) begin
	case(state)
		`PROC_RESET:begin
			ucode_seq_addr <= `UCODE_NO_INSTRUCTION;
			ProgCount <= 'hFFF0;//TODO: Implement Segmentation and set to zero
			HALT <= 0;
			ERROR <= 0;
			SIMPLE_MICRO <= 0;
			reg_write_we <= 1;
			instruction_size_init <= 1;
			state <= `PROC_IF_STATE_ENTRY;
		end
		`PROC_HALT_STATE:begin
		end
		`PROC_IF_STATE_ENTRY:begin
			BHE <= 0;
			external_address_bus <= {4'b0,ProgCount};
			IOMEM <= 0;
			read <= 0;
			write <= 1;
			reg_write_we <= 1;
			state <= `PROC_IF_WRITE_CIR;
			reg_write_in_sel <= 2'b00;
		end
		`PROC_IF_WRITE_CIR:begin
			`ifdef DEBUG_PC_ADDRESS
				/* Weird (possible bug) where even though the
				* testbench stop the clock after ERROR gets
				* raised the logic for the rising edge still
				* gets triggered printing this debug message. */
				if(ERROR!=1)begin
					if(instruction_size==1)
						$display("Fetched instruction at %0x",ProgCount - 1);
					else
						$display("Fetched instruction at %0x",ProgCount - 0);
				end
			`endif
			/*I built the entire decode stage with CIR
			* being big endian so just convert it here*/

			if(instruction_size==1)begin
				/*Half on CIR half on this address */
				state <= `PROC_DE_STATE_ENTRY;
				if(ProgCount[0:0]==1)begin
					CIR <= {CIR[7:0],external_data_bus[15:8]};
				end else begin
					CIR <= {CIR[7:0],external_data_bus[7:0]};
				end
				ProgCount <= ProgCount+1;
			end else begin
				if(ProgCount[0:0]==1)begin
					/* Half on this address half on the next*/
					ProgCount <= ProgCount+1;
					CIR[15:8] <= external_data_bus[15:8];
					state <= `PROC_IF_STATE_EXTRA_FETCH_SET;
				end else begin
					/* Both on this address! */
					ProgCount <= ProgCount+2;
					CIR <= {external_data_bus[7:0],external_data_bus[15:8]};
					state <= `PROC_DE_STATE_ENTRY;
				end
			end

		end
		`PROC_IF_STATE_EXTRA_FETCH_SET:begin
			external_address_bus <= {4'b0,ProgCount};
			BHE <= 0;
			state <= `PROC_IF_STATE_EXTRA_FETCH;
		end
		`PROC_IF_STATE_EXTRA_FETCH:begin
			CIR[7:0] <= external_data_bus[7:0];
			ProgCount <= ProgCount+1;
			state <= `PROC_DE_STATE_ENTRY;
		end
		`PROC_DE_STATE_ENTRY:begin
			external_address_bus <= {4'b0,ProgCount};
			if(SIMPLE_MICRO==0)begin
				/*This flag is set at reset and jump because
				 * at IF we need to know the size of the
				 * previous instruction (specifically if it was
				 * a single byte and the value would be
				 * incorrect in both cases. So when it gets
				 * set reset it only at the start of the next
				 * 8086 instruction */
				instruction_size_init <= 0;

				/* We cannot set these directly within
				* microcode so don't overwrite useful values
				* each time the next microcode is executed.
				* Note this still allows to set initial values
				* at the start of the microcode */
				PARAM1 <= DE_PARAM1;
				PARAM2 <= DE_PARAM2;
			end
			ERROR <= DE_ERROR;
			HALT <= DE_HALT;
			reg_read_port1_addr <= DE_reg_read_port1_addr;
			reg_read_port2_addr <= DE_reg_read_port2_addr;
			reg_write_addr <= DE_reg_write_addr;
			if ( (ucode_seq_addr==`UCODE_NO_INSTRUCTION) && (ucode_seq_addr_entry!=`UCODE_NO_INSTRUCTION) )begin
				/*switch to microcode decoding*/
				ucode_seq_addr <= ucode_seq_addr_entry;
				SIMPLE_MICRO <= 1;
				/*keep state the same and rerun decode this time with all the data from the microcode rom*/
			end else begin
				state <= next_state;
			end
		end
		`PROC_DE_LOAD_REG_TO_PARAM:begin
			PARAM2<=reg_read_port2_data;
			case(IN_MOD)
				3'b000,3'b001,3'b010: state <= `PROC_MEMIO_READ;
				default:              state <= `PROC_EX_STATE_ENTRY;
			endcase
		end
		`PROC_DE_LOAD_8_PARAM:begin
			if(opcode_size==0)begin
				if({Sbit,Wbit}==2'b11)begin
					/*signed "16bit" read*/
					PARAM1 <= {{8{CIR[7:7]}},CIR[7:0]};
				end else begin
					PARAM1[7:0] <= CIR[7:0];
				end
				case(IN_MOD)
					3'b000,3'b001,3'b010: state <= `PROC_MEMIO_READ;
					default:              state <= `PROC_EX_STATE_ENTRY;
				endcase
			end else begin
				if(ProgCount[0:0]==1)begin
					if({Sbit,Wbit}==2'b11)begin
						/*signed "16bit" read*/
						PARAM1 <= {{8{external_data_bus[15:15]}},external_data_bus[15:8]};
					end else begin
						PARAM1[7:0] <= external_data_bus[15:8];
					end
				end else begin
					if({Sbit,Wbit}==2'b11)begin
						/*signed "16bit" read*/
						PARAM1 <= {{8{external_data_bus[7:7]}},external_data_bus[7:0]};
					end else begin
						PARAM1[7:0] <= external_data_bus[7:0];
					end
				end
				ProgCount <= ProgCount+1;
				case(IN_MOD)
					3'b000,3'b001,3'b010: state <= `PROC_MEMIO_READ;
					default:              state <= `PROC_EX_STATE_ENTRY;
				endcase
			end
		end
		`PROC_DE_LOAD_16_PARAM:begin
			if(opcode_size==0)begin
				PARAM1[7:0] <= CIR[7:0];
				if(ProgCount[0:0]==1)begin
					PARAM1[15:8] <= external_data_bus[15:8];
				end else begin
					PARAM1[15:8] <= external_data_bus[7:0];
				end
				ProgCount <= ProgCount+1;
				case(IN_MOD)
					3'b000,3'b001,3'b010: state <= `PROC_MEMIO_READ;
					default:              state <= `PROC_EX_STATE_ENTRY;
				endcase
			end else begin
				if(ProgCount[0:0]==1)begin
					ProgCount <= ProgCount+1;
					PARAM1[7:0] <= external_data_bus[15:8];
					state <= `PROC_DE_LOAD_16_EXTRA_FETCH_SET;
				end else begin
					PARAM1 <= external_data_bus;
					ProgCount <= ProgCount+2;
					case(IN_MOD)
						3'b000,3'b001,3'b010: state <= `PROC_MEMIO_READ;
						default:              state <= `PROC_EX_STATE_ENTRY;
					endcase
				end
			end
		end
		`PROC_DE_LOAD_16_EXTRA_FETCH_SET:begin
			external_address_bus <= {4'b0,ProgCount};
			state <= `PROC_DE_LOAD_16_EXTRA_FETCH;
		end
		`PROC_DE_LOAD_16_EXTRA_FETCH:begin
			ProgCount <= ProgCount+1;
			PARAM1[15:8] <= external_data_bus[7:0];
			case(IN_MOD)
				3'b000,3'b001,3'b010: state <= `PROC_MEMIO_READ;
				default:              state <= `PROC_EX_STATE_ENTRY;
			endcase
		end
		`PROC_MEMIO_READ:begin
			/*Decode MOD R/M, read the data and place it to PARAM1*/
			case (IN_MOD)
				3'b000,
					3'b001,
					3'b010:begin
					case (RM)
						3'b000:begin
							/*[BX]+[SI]*/
							`invalid_instruction
						end
						3'b001:begin
							/*[BX]+[SI]*/
							`invalid_instruction
						end
						3'b010:begin
							/*[BP]+[SI]*/
							`invalid_instruction
						end
						3'b011:begin
							/*[BP]+[DI]*/
							`invalid_instruction
						end
						3'b100:begin
							/*[SI]*/
							reg_read_port1_addr <= 4'b1110;
							state <= `PROC_MEMIO_READ_SETADDR;
						end
						3'b101:begin
							/*[DI]*/
							reg_read_port1_addr <= 4'b1111;
							state <= `PROC_MEMIO_READ_SETADDR;
						end
						3'b110:begin
							/*d16 */
							`invalid_instruction
						end
						3'b111:begin
							/*[BX]*/
							reg_read_port1_addr <= 4'b1011;
							state <= `PROC_MEMIO_READ_SETADDR;
						end
					endcase
					if(IN_MOD!=3'b000)begin
						/*Actually check if 01 and add the 8bits or if 10 add the 16bits ....*/
						`invalid_instruction;
					end
				end
				3'b110:begin /* SP Indirect read*/
					reg_read_port1_addr <= 4'b1100;
					state <= `PROC_MEMIO_READ_SETADDR;
				end
				default:begin
					`invalid_instruction
				end
			endcase
		end
		`PROC_MEMIO_READ_SETADDR:begin
			if(memio_address_select==0)
				external_address_bus <= {4'b0,reg_read_port1_data[15:0]};
			else
				external_address_bus <= {4'b0,ALU_1O};
			state <= (memio_address_select?ALU_1O[0:0]:reg_read_port1_data[0:0])?`PROC_MEMIO_GET_UNALIGNED_DATA:`PROC_MEMIO_GET_ALIGNED_DATA;
		end
		`PROC_MEMIO_GET_ALIGNED_DATA:begin
			PARAM2 <= (Wbit==1)? external_data_bus : {8'b0,external_data_bus[7:0]} ;
			state <= `PROC_EX_STATE_ENTRY;
		end
		`PROC_MEMIO_GET_UNALIGNED_DATA:begin
			PARAM2 <= {8'b0,external_data_bus[15:8]};
			if(Wbit==1) begin
				state <= `PROC_MEMIO_GET_SECOND_BYTE;
			end else begin
				state <= `PROC_EX_STATE_ENTRY;
			end
		end
		`PROC_MEMIO_GET_SECOND_BYTE:begin
			external_address_bus <= external_address_bus+1;
			state <= `PROC_MEMIO_GET_SECOND_BYTE1;
		end
		`PROC_MEMIO_GET_SECOND_BYTE1:begin
			PARAM2[15:8] <= external_data_bus[7:0];
			state <= `PROC_EX_STATE_ENTRY;
		end
		`PROC_EX_STATE_ENTRY:begin
			external_address_bus <= {4'b0,ProgCount};
			FLAGS[7:0] <= ALU_1FLAGS[7:0];
			case(OUT_MOD)
				3'b000,
					3'b001,
					3'b010 : begin
					if(memio_address_select==1)
						state <= `PROC_MEMIO_WRITE;
					else
						case (RM) /* Duplicate code with write... */
							3'b000:begin
								/*[BX]+[SI]*/
								`invalid_instruction
							end
							3'b001:begin
								/*[BX]+[SI]*/
								`invalid_instruction
							end
							3'b010:begin
								/*[BP]+[SI]*/
								`invalid_instruction
							end
							3'b011:begin
								/*[BP]+[DI]*/
								`invalid_instruction
							end
							3'b100:begin
								/*[SI]*/
								reg_read_port1_addr <= 4'b1110;
								state <= `PROC_MEMIO_WRITE;
							end
							3'b101:begin
								/*[DI]*/
								reg_read_port1_addr <= 4'b1111;
								state <= `PROC_MEMIO_WRITE;
							end
							3'b110:begin
								/*d16 */
								`invalid_instruction
							end
							3'b111:begin
								/*[BX]*/
								reg_read_port1_addr <= 4'b1011;
								state <= `PROC_MEMIO_WRITE;
							end
						endcase
				end
				3'b011:begin
					reg_write_we <= 0;
					if (ucode_seq_addr==`UCODE_NO_INSTRUCTION)
						state <= `PROC_IF_STATE_ENTRY;
					else
						state <= `PROC_NEXT_MICROCODE;
				end
				3'b100:begin /*No output*/
					if (ucode_seq_addr==`UCODE_NO_INSTRUCTION)
						state <= `PROC_IF_STATE_ENTRY;
					else
						state <= `PROC_NEXT_MICROCODE;
				end
				3'b101:begin /* Program Counter*/
					ProgCount <= ALU_1O[15:0];
					instruction_size_init <= 1;
					if (ucode_seq_addr==`UCODE_NO_INSTRUCTION)
						state <= `PROC_IF_STATE_ENTRY;
					else
						state <= `PROC_NEXT_MICROCODE;
				end
				3'b110:begin /* SP Indirect write*/
					reg_read_port1_addr <= 4'b1100;
					state <= `PROC_MEMIO_WRITE;
				end
				3'b111:begin /* Write to PRAM1 (for microcode calculations) */
					PARAM1 <= ALU_1O;
					if (ucode_seq_addr==`UCODE_NO_INSTRUCTION)
						state <= `PROC_IF_STATE_ENTRY;
					else
						state <= `PROC_NEXT_MICROCODE;
				end
				default:begin
					`invalid_instruction
				end
			endcase
		end
		`PROC_MEMIO_WRITE:begin
			/* if memio_address_select == 0  ADDRESS: reg_read_port1_data   DATA:ALU1_O */
			/* if memio_address_select == 1  ADDRESS: ALU1_O                DATA: reg_read_port1_data */
			`ifdef DEBUG_MEMORY_WRITES
				$display("Writing at %04x , %04x",reg_read_port1_data,ALU_1O);
			`endif
			if(memio_address_select==0)
				external_address_bus <= {4'b0,reg_read_port1_data[15:0]};
			else
				external_address_bus <= {4'b0,ALU_1O};

			IOMEM <= MEM_OR_IO;
			state <= (Wbit==0) ? `PROC_MEMIO_PUT_BYTE : (reg_read_port1_data[0:0]?`PROC_MEMIO_PUT_UNALIGNED_16BIT_DATA:`PROC_MEMIO_PUT_ALIGNED_16BIT_DATA) ;
		end
		`PROC_MEMIO_PUT_UNALIGNED_16BIT_DATA:begin
			read <= 1;
			BHE <= 0;
			if(memio_address_select==0)
				data_bus_output_register <= {ALU_1O[7:0],ALU_1O[15:8]};
			else
				data_bus_output_register <= {reg_read_port1_data[7:0],reg_read_port1_data[15:8]};
			state <= `PROC_MEMIO_PUT_UNALIGNED_PREP_NEXT;
		end
		`PROC_MEMIO_PUT_UNALIGNED_PREP_NEXT:begin
			write <= 0;
			state <= `PROC_MEMIO_PUT_UNALIGNED_PREP_NEXT2;
		end
		`PROC_MEMIO_PUT_UNALIGNED_PREP_NEXT2:begin
			write <= 1;
			external_address_bus <= external_address_bus+1;
			BHE <= 1;
			state <= `PROC_MEMIO_WRITE_EXIT;
		end
		`PROC_MEMIO_PUT_ALIGNED_16BIT_DATA:begin
			read <= 1;
			data_bus_output_register <= {ALU_1O[15:8],ALU_1O[7:0]};
			state <= `PROC_MEMIO_WRITE_EXIT;
		end
		`PROC_MEMIO_PUT_BYTE:begin
			read <= 1;
			state <= `PROC_MEMIO_WRITE_EXIT;
			if((memio_address_select?ALU_1O[0:0]:reg_read_port1_data[0:0])==0) begin
				BHE <= 1;
				if(memio_address_select==0)
					data_bus_output_register <= {8'b0,ALU_1O[7:0]};
				else
					data_bus_output_register <= {8'b0,reg_read_port1_data[7:0]};
			end else begin
				BHE <= 0;
				if(memio_address_select==0)
					data_bus_output_register <= {ALU_1O[7:0],8'b0};
				else
					data_bus_output_register <= {reg_read_port1_data[7:0],8'b0};
			end
		end
		`PROC_MEMIO_WRITE_EXIT:begin
			write <= 0;
			if (ucode_seq_addr==`UCODE_NO_INSTRUCTION)
				state <= `PROC_IF_STATE_ENTRY;
			else
				state <= `PROC_NEXT_MICROCODE;
		end
		`PROC_NEXT_MICROCODE:begin
			read <= 0;
			write <= 1; // maybe we are coming from MEMIO_WRITE
			BHE <= 0;
			ucode_seq_addr <= ucode_seq_addr_entry; /*Reused for next address*/
			if( ucode_seq_addr_entry == `UCODE_NO_INSTRUCTION )begin
				/*Finished microcode*/
				SIMPLE_MICRO <= 0;
				state <= `PROC_IF_STATE_ENTRY;
			end else begin
				state <= `PROC_DE_STATE_ENTRY;
			end
			reg_write_we <= 1;
		end
		default:begin
		end
	endcase
end
`undef invalid_instruction


endmodule