/* top.v - Implements FPGA and Board specific circuitry This file is part of the 9086 project. Copyright (c) 2023 Efthymios Kritikos This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program. If not, see . */ `include "error_header.v" module fpga_top( input clk48, input user_button, // output reset_n, output rgb_led0_r, output rgb_led0_g, output rgb_led0_b, inout gpio_0,/*sda*/ output gpio_1 /*scl*/ ); wire HALT; wire [`ERROR_BITS-1:0]ERROR; wire [19:0] address_bus; wire [15:0] data_bus_read,data_bus_write; wire rd,wr,BHE,IOMEM; system system( /* MISC */ clk48,reset /* MEMORY / IO */ ,address_bus,data_bus_read,data_bus_write,BHE,rd,wr,IOMEM,HALT,ERROR ); reg [2:0]rgb_led_color; assign rgb_led0_r=rgb_led_color[0]; assign rgb_led0_g=rgb_led_color[1]; assign rgb_led0_b=rgb_led_color[2]; // A bit useless since if the cpu ERORRS out or HALTS it will continue executing anyway //always @(HALT or ERROR or user_button) begin // if (HALT==1) begin // /* yellow */ // rgb_led_color<=3'b100; // end else if (ERROR != `ERROR_BITS'b0) begin // /* red */ // rgb_led_color<=3'b110; // end else begin // /* green */ // rgb_led_color<=3'b101; // end //end // Create a 27 bit register reg [26:0] counter = 0; // Every positive edge increment register by 1 always @(posedge clk48) begin counter <= counter + 1; end /*** RESET CIRCUIT ***/ reg reset=0; reg [1:0] state=0; always @(posedge counter[3]) begin if(user_button==0) state=2'b00; case (state) 2'b00:begin reset<=0; state<=2'b01; end 2'b01:begin reset<=1; state<=2'b10; end default: begin end endcase end always @(negedge wr) begin if(IOMEM==1'b1 && address_bus[7:0]==8'hA5 )begin //disp_write_cache[disp_cache_end]<=data_bus_write[7:0]; disp_write_cache[disp_cache_end]<=data_bus_write[15:8]; disp_cache_end<=disp_cache_end+5'd1; end else if(IOMEM==1'b1 && address_bus[7:0]==8'hB0 )begin if(data_bus_write[0:0]==1) rgb_led_color=3'b000; else rgb_led_color=3'b111; end end //------------------------------------------// // Cache to allow the slow display to have a // chance to keep up with the relentless CPU reg [4:0] disp_cache_start=0; reg [4:0] disp_cache_end=0; reg [7:0] disp_write_cache [31:0]; reg ascii_state=0; always @(posedge clk48)begin case (ascii_state) 1'b0:begin if(ascii_data_ready&disp_cache_start!=disp_cache_end)begin ascii_data<=disp_write_cache[disp_cache_start]; disp_cache_start<=disp_cache_start+5'd1; ascii_data_write_req<=1; ascii_state<=1'b1; end end 1'b1:begin if(!ascii_data_ready)begin ascii_data_write_req<=0; ascii_state<=1'b0; end end default: begin end endcase end wire I2C_SPEED=counter[7]; // Display driver wire ascii_data_ready; reg ascii_data_write_req=0; reg [7:0] ascii_data; ascii_to_HD44780_driver LCD_DRIVER( /* system */ I2C_SPEED, 1'b1, /* Data Input */ ascii_data_ready, ascii_data_write_req, ascii_data, /* write circuitry */ !pcf_busy, pcf_write_req, pcf_data, pcf_command_data ); // Port expander driver wire pcf_write_req,pcf_command_data,pcf_busy; wire [3:0]pcf_data; wire [7:0]i2c_data; pcf8574_for_HD44780 PCF8574_driver( .clock(I2C_SPEED), .pcf_write_req(pcf_write_req), .pcf_command_data(pcf_command_data), .pcf_data(pcf_data), .pcf_busy(pcf_busy), .new_backlight(1'b0), .backlight_update(1'b0), .I2C_BUSY(I2C_BUSY), .I2C_SEND(I2C_SEND), .i2c_data(i2c_data) ); // I2C driver wire SCL,SDA,I2C_BUSY,I2C_SEND; assign gpio_1=SCL; assign gpio_0=SDA; reg [7:0]i2c_data; I2C_driver i2c_driver( .clock(I2C_SPEED), .SDA_(SDA), .SCL(SCL), .address(7'h27), .I2C_BUSY(I2C_BUSY), .I2C_SEND(I2C_SEND), .i2c_data(i2c_data), ); endmodule