`include "proc_state_def.v"
`include "alu_header.v"

module mux4 (in1,in2,in3,in4, sel,out); 
input [0:1] sel;
parameter WIDTH=16;
input [WIDTH-1:0] in1,in2,in3,in4;
output [WIDTH-1:0] out;
assign out = (sel == 'b00) ? in1 :
	(sel == 'b01) ? in2 :
	(sel == 'b10) ? in3 :
	in4;
endmodule

module processor ( input clock, input reset, output reg [19:0] external_address_bus, inout [15:0] external_data_bus,output reg read, output reg write, output reg HALT,output reg ERROR);

/*** Global Definitions ***/
// State
reg [3:0] state;

// Registers
reg [19:0] ProgCount;
reg [15:0] CIR;
reg [15:0] PARAM1;
reg [15:0] PARAM2;
reg unaligned_access;
reg [1:0]IN_MOD;
reg [2:0]IN_RM;
reg Wbit;

// Execution units
reg [1:0] in1_sel;
reg [1:0] in2_sel;
reg [1:0] out_sel;

/*** RESET LOGIC ***/
always @(negedge reset) begin
	if (reset==0) begin
		@(posedge clock);
		state=`PROC_HALT_STATE;
		ProgCount=0;//TODO: Reset Vector
		HALT=0;
		reg_write_we=1;
		reg_read_oe=1;
		unaligned_access=0;
		ALU_1OE=1;
		@(posedge reset)
		@(negedge clock);
		state=`PROC_IF_STATE_ENTRY;
		IN_MOD=2'b11;
	end
end

/*** ALU and EXEC stage logic ***/

//Architectural Register file
reg [3:0] reg_write_addr;
reg [15:0] reg_write_data;
reg reg_write_we;
reg [3:0] reg_read_addr;
reg [15:0] reg_read_data;
reg reg_read_oe;
register_file register_file(reg_write_addr,reg_write_data,reg_write_we,reg_read_addr,reg_read_data,reg_read_oe);

//ALU
mux4 #(.WIDTH(16)) MUX16_1A(
	PARAM1,
	reg_read_data,
	16'b0,
	16'b0,
	in1_sel,
	ALU_1A);

mux4 #(.WIDTH(16)) MUX16_1B(
	PARAM2,
	reg_read_data,
	16'b0,
	16'b0,
	in2_sel,
	ALU_1B);

wire [15:0] ALU_1A;
wire [15:0] ALU_1B;
wire [15:0] ALU_1O;
reg [`ALU_OP_BITS-1:0]ALU_1OP;
reg ALU_1OE;
ALU ALU(ALU_1A,ALU_1B,ALU_1OE,ALU_1O,ALU_1OP);

/*** Processor stages ***/

`define invalid_instruction state=`PROC_IF_STATE_ENTRY;ERROR=1;IN_MOD=2'b11;
`define start_aligning_instruction if(unaligned_access==0)begin ProgCount=ProgCount+1; external_address_bus <= ProgCount; end /*we normally don't advance PC in case of singly byte unaligning instructions leasving us with two instructions in one read so do that here*/
`define start_unaligning_instruction unaligned_access=~unaligned_access;

always @(negedge clock) begin
	case(state)
		`PROC_IF_WRITE_CIR:begin
			if(unaligned_access)begin
				CIR[15:8] <= external_data_bus[7:0];
				ProgCount=ProgCount+1;
				state=`PROC_IF_STATE_EXTRA_FETCH_SET;
			end else begin
				CIR <= external_data_bus;
				state=`PROC_DE_STATE_ENTRY;
			end
		end
		`PROC_IF_STATE_EXTRA_FETCH:begin
			CIR[7:0] <= external_data_bus[15:8];
			state=`PROC_DE_STATE_ENTRY;
		end
		`PROC_EX_STATE_EXIT:begin
			case(out_sel)
				2'b11:begin
					reg_write_we=0;
					state=`PROC_IF_STATE_ENTRY;
				end
				default:begin
					`invalid_instruction
				end
			endcase
		end
		`PROC_DE_LOAD_16_EXTRA_FETCH_SET:begin
			external_address_bus = ProgCount;
			state=`PROC_DE_LOAD_16_EXTRA_FETCH;
		end
		`PROC_MEMIO_SETADDR:begin
			external_address_bus = {1'b0,reg_read_data[15:1]};
			state=reg_read_data[0:0]?`PROC_MEMIO_GET_UNALIGNED_DATA:`PROC_MEMIO_GET_ALIGNED_DATA;
		end
	endcase
end

always @(posedge clock) begin
	case(state)
		`PROC_HALT_STATE:begin
		end
		`PROC_IF_STATE_ENTRY:begin
			ERROR=0;
			external_address_bus <= ProgCount;
			read <= 0;
			write <= 1;
			reg_read_oe=1;
			reg_write_we=1;
			ALU_1OE=1;
			state=`PROC_IF_WRITE_CIR;
		end
		`PROC_IF_STATE_EXTRA_FETCH_SET:begin
			external_address_bus <= ProgCount;
			state=`PROC_IF_STATE_EXTRA_FETCH;
		end
		/* 0 0 0 0  0 0 0 0 | 0 0 0 0  0 0 0 0 | 0 0 0 0  0 0 0 0 | 0 0 0 0  0 0 0 0 */
		/* AFTER THE IF STAGE WE HAVE THE FRIST BYTE OF THE
		* INSTRUCTION ADN THE ONE FOLLOWING, ALLIGNED CORRECTLY TO
		* CIR */
		`PROC_DE_STATE_ENTRY:begin
			case(CIR[15:10])
				6'b000001 : begin
					/* ADD, ... */
					if ( CIR[9:9] == 0 )begin
						/*       Add Immediate word/byte to accumulator           */
						/* 0 0 0 0  0 1 0 W |       DATA       |     DATA if W   |*/
						Wbit=CIR[8:8];
						if(Wbit)
							`start_unaligning_instruction
						else
							`start_aligning_instruction
						IN_MOD=2'b11;
						in1_sel=2'b00;
						in2_sel=2'b01;
						out_sel=2'b11;
						reg_read_addr={CIR[8:8],3'b000};
						reg_write_addr={CIR[8:8],3'b000};
						reg_read_oe=0;
						ALU_1OE=0;
						ALU_1OP=`ALU_OP_ADD;
						if(CIR[8:8]==1)
							state=`PROC_DE_LOAD_16_PARAM;
						else begin
							`invalid_instruction /*do 8bit loads*/
						end
					end else begin
						`invalid_instruction
					end
				end
				6'b100000 : begin
					/* ADD, ADC, SUB, SBB, CMP , AND, ... */
					case (CIR[5:3])
						3'b000 : begin
							/* Add Immediate word/byte to register/memory */
							/* 1 0 0 0  0 0 S W | MOD 0 0  0  R/M  |     < DISP LO >  |     < DISP HI >   |      DATA        |      DATA if W    |    */
							`start_aligning_instruction
							IN_MOD=2'b11;
							in1_sel=2'b00;
							in2_sel=2'b01;
							out_sel=CIR[7:6];
							reg_read_addr={CIR[8:8],CIR[2:0]};
							reg_write_addr={CIR[8:8],CIR[2:0]};
							reg_read_oe=0;
							ALU_1OE=0;
							ALU_1OP=`ALU_OP_ADD;
							state=`PROC_DE_LOAD_16_PARAM;
							if(CIR[8:8]==1)
								state=`PROC_DE_LOAD_16_PARAM;
							else begin
								`invalid_instruction /*do 8bit loads*/
							end
						end
						default:begin
							`invalid_instruction
						end
					endcase
				end
				6'b101100,
					6'b101101:begin
					/*        MOV - Move Immediate byte to register            */
					/* 1 0 1 1  W  REG  |       DATA       |     DATA if W    |*/
					Wbit=CIR[11:11];
					if(Wbit)
						`start_unaligning_instruction
					else
						`start_aligning_instruction
					IN_MOD=2'b11;
					in1_sel=2'b00;
					in2_sel=2'b00;
					out_sel=2'b11;
					reg_write_addr={1'b0,CIR[10:8]};
					PARAM1[7:0]=CIR[7:0];
					PARAM2=0;
					ALU_1OE=0;
					ALU_1OP=`ALU_OP_ADD;
					state=`PROC_EX_STATE_ENTRY;
				end
				6'b101110,
					6'b101111 : begin
					/*MOV - Move Immediate word to register*/
					Wbit=CIR[11:11];
					if(Wbit)
						`start_unaligning_instruction
					else
						`start_aligning_instruction
					IN_MOD=2'b11;
					in1_sel=2'b00;
					in2_sel=2'b00;
					out_sel=2'b11;
					reg_write_addr={1'b1,CIR[10:8]};
					ALU_1OE=0;
					ALU_1OP=`ALU_OP_ADD;
					PARAM2=0;
					state=`PROC_DE_LOAD_16_PARAM;
				end

				6'b100010 : begin
					/*                      MOV - Reg/Mem to/from register                        */
					/* 1 0 0 0  1 0 D W | MOD   REG   REG  |    < DISP LO >   |    < DISP HI >   |*/
					`start_aligning_instruction
					IN_MOD=CIR[7:6];
					IN_RM=CIR[2:0];
					Wbit=CIR[8:8];
					if(CIR[9:9] == 1)begin
						/* to reg */
						IN_MOD=CIR[7:6];
						if(IN_MOD==2'b11)begin
							in1_sel=2'b01;
							reg_read_addr=CIR[2:0];
						end else begin
							in1_sel=2'b00;
						end
						in2_sel=2'b00;
						out_sel=2'b11;
						reg_write_addr={CIR[8:8],CIR[5:3]};
					end else begin
						`invalid_instruction
					end

					ALU_1OE=0;
					ALU_1OP=`ALU_OP_ADD;
					PARAM2=0;
					state=`PROC_DE_LOAD_16_PARAM;
					if ( IN_MOD == 2'b11 )
						state=`PROC_EX_STATE_ENTRY;
					else
						state=`RPOC_MEMIO_READ;
				end
				6'b010000,//INC
				6'b010001,//INC
				6'b010010,//DEC
				6'b010011:begin//DEC
					/* DEC - Decrement Register */
					/*   | 0 1 0 0  1  REG  |   */
					/* INC - Increment Register */
					/*   | 0 1 0 0  0  REG  |   */
					`start_unaligning_instruction
					in1_sel=2'b01;
					in2_sel=2'b00;
					out_sel=2'b11;
					IN_MOD=2'b11;
					PARAM2=1;
					reg_read_addr={1'b1,CIR[10:8]};
					reg_write_addr={1'b1,CIR[10:8]};
					reg_read_oe=0;
					ALU_1OE=0;
					if(CIR[11:11]==0)
						ALU_1OP=`ALU_OP_ADD;
					else
						ALU_1OP=`ALU_OP_SUB;
					state=`PROC_EX_STATE_ENTRY;
				end
				6'b111111 : begin
					/* INC */
					if (CIR[9:9] == 1 ) begin
						case (CIR[5:3])
							3'b000 :begin
								/*                          INC - Register/Memory                            */
								/* 1 1 1 1  1 1 1 W | MOD 0 0  0  R/M  |    < DISP LO>    |    < DISP HI>    */
								`start_aligning_instruction
								IN_MOD=CIR[7:6];
								in1_sel=2'b00;/* number 1 */
								in2_sel=(CIR[7:6]==2'b11)? 2'b01 : 2'b00;
								out_sel=CIR[7:6];
								PARAM1=1;
								reg_read_addr={1'b0,CIR[2:0]};
								reg_write_addr={1'b0,CIR[2:0]};
								reg_read_oe=0;
								ALU_1OE=0;
								ALU_1OP=`ALU_OP_ADD;
								if ( CIR[7:6] == 2'b11 )
									state=`PROC_EX_STATE_ENTRY;
								else
									state=`RPOC_MEMIO_READ;
							end
							default:begin
								`invalid_instruction
							end
						endcase
					end else begin
						`invalid_instruction
					end
				end
				6'b111101 : begin
					/*HLT, CMC, TEST, NOT, NEG, MUL, IMUL, .... */
					case (CIR[9:8])
						2'b00:begin
							/*     HLT - Halt     */
							/* 1 1 1 1  0 1 0 0 | */
							`start_unaligning_instruction
							IN_MOD=2'b11;
							HALT=1;
							state=`PROC_HALT_STATE;
						end
						default:begin
							`invalid_instruction;
						end
					endcase

				end
				default:begin
					`invalid_instruction
				end
			endcase
		end
		`PROC_DE_LOAD_16_PARAM:begin
			if(unaligned_access==1)begin
				PARAM1[7:0] = external_data_bus[7:0];
				ProgCount=ProgCount+1;
				state=`PROC_DE_LOAD_16_EXTRA_FETCH_SET;
			end else begin
				PARAM1[7:0] = external_data_bus[15:8];
				PARAM1[15:8] = external_data_bus[7:0];
				ProgCount=ProgCount+1;
				state=`PROC_EX_STATE_ENTRY;
			end
		end
		`PROC_DE_LOAD_16_EXTRA_FETCH:begin
			PARAM1[15:8] = external_data_bus[15:8];
			state=`PROC_EX_STATE_ENTRY;
		end
		`RPOC_MEMIO_READ:begin
			/*Decode MOD R/M, read the data and place it to PARAM1*/
			case (IN_RM)
				3'b000:begin
					/*[BX]+[SI]*/
					`invalid_instruction
				end
				3'b001:begin
					/*[BX]+[SI]*/
					`invalid_instruction
				end
				3'b010:begin
					/*[BP]+[SI]*/
					`invalid_instruction
				end
				3'b011:begin
					/*[BP]+[DI]*/
					`invalid_instruction
				end
				3'b100:begin
					/*[SI]*/
					reg_read_addr=4'b1110;
					reg_read_oe=0;
					state=`PROC_MEMIO_SETADDR;
				end
				3'b101:begin
					/*[DI]*/
					reg_read_addr=4'b1111;
					reg_read_oe=0;
					state=`PROC_MEMIO_SETADDR;
				end
				3'b110:begin
					/*d16 */
					`invalid_instruction
				end
				3'b111:begin
					/*[BX]*/
					reg_read_addr=4'b1011;
					reg_read_oe=0;
					state=`PROC_MEMIO_SETADDR;
				end
			endcase
			if(IN_MOD!=2'b00)begin
				/*Actually check if 01 and add the 8bits or if 10 add the 16bits ....*/
				`invalid_instruction;
		       end

	       end
	       `PROC_MEMIO_GET_ALIGNED_DATA:begin
		       PARAM1=(Wbit==1)? external_data_bus : {8'b00000000,external_data_bus[15:8]} ;
		       state=`PROC_EX_STATE_ENTRY;
	       end
	       `PROC_MEMIO_GET_UNALIGNED_DATA:begin
		       if(Wbit==1) begin
			       `invalid_instruction //easy to implement, get the other byte from the next address
		       end else begin
			       PARAM1={8'b00000000,external_data_bus[7:0]};
			       state=`PROC_EX_STATE_ENTRY;
		       end
	       end
	       `PROC_EX_STATE_ENTRY:begin
		       reg_write_data=ALU_1O;
		       state=`PROC_EX_STATE_EXIT;
		       ERROR=0;
	       end
       endcase
end


endmodule