The OrangeCrab r0.2.1 has been configured with an I2C bus controller and LiteDRAM for the DDR3 memory that is on-board.

This is a block diagram of the system:

<img width="400" style=" margin: 10px 0px 10px 10px;" alt="overview diagram" src="readme_files/overview_diagram.svg">

and inside the FPGA:

<img width="700" style=" margin: 10px 0px 10px 10px;" alt="system diagram" src="readme_files/system_diagram.svg">

and this is the hardware setup during development:

<img width="700" style=" margin: 10px 0px 10px 10px;" alt="Hardware picture" src="readme_files/picture.png">

You can find some configuration options in the [./config.mk](./config.mk)