From fa62b07c14ac9fad087db8bab707a5de1b02e7ee Mon Sep 17 00:00:00 2001 From: "(Tim) Efthimis Kritikos" Date: Sun, 12 Nov 2023 03:13:22 +0000 Subject: [PATCH] Removed probably unnecessary high impedance case yosys was complaining about in registers.v --- system/registers.v | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/system/registers.v b/system/registers.v index a1ca666..33b6956 100644 --- a/system/registers.v +++ b/system/registers.v @@ -32,11 +32,11 @@ input write_port1_we; reg [15:0] registers [7:0]; -assign read_port1_data[15:8] = read_port1_addr[3:3] ? registers[read_port1_addr[2:0]][15:8] : 8'hz ; +assign read_port1_data[15:8] = read_port1_addr[3:3] ? registers[read_port1_addr[2:0]][15:8] : 8'h0 ; assign read_port1_data[7:0] = ( read_port1_addr[3:3] ? registers[read_port1_addr[2:0]][7:0] : ( read_port1_addr[2:2] ? registers[ {1'b0,read_port1_addr[1:0]} ][15:8] : registers[ {1'b0,read_port1_addr[1:0]} ][7:0] ) ); -assign read_port2_data[15:8] = read_port2_addr[3:3] ? registers[read_port2_addr[2:0]][15:8] : 8'hz ; +assign read_port2_data[15:8] = read_port2_addr[3:3] ? registers[read_port2_addr[2:0]][15:8] : 8'h0 ; assign read_port2_data[7:0] = ( read_port2_addr[3:3] ? registers[read_port2_addr[2:0]][7:0] : ( read_port2_addr[2:2] ? registers[ {1'b0,read_port2_addr[1:0]} ][15:8] : registers[ {1'b0,read_port2_addr[1:0]} ][7:0] ) );