From e8b84a38b6ed2972742518a3e82122a2cede2f04 Mon Sep 17 00:00:00 2001
From: "(Tim) Efthimis Kritikos" <efkf@firemail.cc>
Date: Sun, 5 Mar 2023 06:37:07 +0000
Subject: [PATCH] Updated README.md about verilator

---
 README.md | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/README.md b/README.md
index 5d39689..af45e12 100644
--- a/README.md
+++ b/README.md
@@ -14,16 +14,16 @@ A CPU that aims to be binary compatible with the 8086 and with as many optimisat
 * [ ] Has been successfully synthesized
 
 ### Simulating it
-To simulate this project you need Icarus Verilog, bin86, GNU make, xxd and the posix coreutils.
+Both Verilator and Icarus Verilog can be used for simulation. You can select which one you want with the SIM variable on [common.mk](./common.mk)
+Specifically this list shows the software needed and the versions used during development
+
+* Icarus Verilog version 11.0 (stable) OR **(preferred)** Verilator 5.006
+* bin86 : 0.16.21
+* GNU Make : 4.4.1
+* xxd : 2022-01-14
+* GNU coreutils : 9.1
+
 After that you can run `make` on the top level directory and it should build everything and start the simulation
 
-At the time of development the versions used are :
-
-* Icarus Verilog version 11.0 (stable)
-* bin86 version: 0.16.21
-* GNU Make 4.4.1
-* xxd 2022-01-14
-* GNU coreutils 9.1
-
 ### License
 All parts of this project are licensed under the GNU General Public License version 3 or later