diff --git a/system/biu.v b/system/biu.v
index 256d9fa..45d2846 100644
--- a/system/biu.v
+++ b/system/biu.v
@@ -95,8 +95,8 @@ always @(posedge reset) begin
 	biu_state <= `BIU_RESET;
 	/* verilator lint_off BLKSEQ */
 	FIFO_start = `L1_CACHE_SIZE'b0;
+	FIFO_end = `L1_CACHE_SIZE'b0;
 	/* verilator lint_on BLKSEQ */
-	FIFO_end <= `L1_CACHE_SIZE'b0;
 end
 
 reg jump_req_latch;
@@ -111,8 +111,8 @@ always @(posedge clock) begin
 	if ( jump_req_latch ) begin
 		/* verilator lint_off BLKSEQ */
 		FIFO_start = 0;
+		FIFO_end = 0;
 		/* verilator lint_on BLKSEQ */
-		FIFO_end <= 0;
 		INSTRUCTION_ADDRESS <= { 4'b0 , ADDRESS_INPUT };
 		INSTRUCTION_LOCATION <= ADDRESS_INPUT;
 		func <= 1;
@@ -130,6 +130,10 @@ always @(posedge clock) begin
 					DATA_DIR <= 1 ;
 					IOMEM <= MEM_OR_IO;
 					biu_state <= (Wbit==0) ? `BIU_PUT_BYTE : (ADDRESS_INPUT[0:0]?`BIU_PUT_UNALIGNED_16BIT_DATA:`BIU_PUT_ALIGNED_16BIT_DATA) ;
+					INSTRUCTION_ADDRESS <= {4'b0,INSTRUCTION_LOCATION} ;
+					/* verilator lint_off BLKSEQ */
+					FIFO_end=FIFO_start;
+					/* verilator lint_on BLKSEQ */
 				end else if ( read_request ) begin
 					func<=0;
 					DATA_ADDRESS <= { 4'b0 , ADDRESS_INPUT };
@@ -152,7 +156,15 @@ always @(posedge clock) begin
 				end
 
 				`ifdef EARLY_VALID_INSTRUCTION
-				if((Isit1==1) && (FIFO_SIZE!=0) && `EARLY_VALID_INSTRUCTION_)begin
+
+				if(FIFO_start==FIFO_end) begin
+					/*TODO: I would use FIFO_SIZE==0 here or better yet add an else at the
+						end but since FIFO_start and FIFO_end are updated in a blocking
+						manner it seems that the assign statement updating FIFO_SIZE
+						doesn't work. PLEASE CLEAN UP THIS MESS */
+					VALID_INSTRUCTION <= 0;
+					/*TODO: do we need the last of the three parts ?*/
+				end else if((Isit1==1) && (FIFO_SIZE!=0) && `EARLY_VALID_INSTRUCTION_)begin
 					VALID_INSTRUCTION <= 1;
 					INSTRUCTION[31:24] <= INPUT_FIFO[FIFO_start];
 				end else if((fifoIsize==2) && (FIFO_SIZE > `L1_CACHE_SIZE'd1) && `EARLY_VALID_INSTRUCTION_)begin
@@ -172,7 +184,10 @@ always @(posedge clock) begin
 					INSTRUCTION[ 7: 0] <= INPUT_FIFO[FIFO_start+`L1_CACHE_SIZE'd3];
 				end
 				`else
-				if(FIFO_SIZE>`L1_CACHE_SIZE'd3)begin
+				if(FIFO_start==FIFO_end) begin
+					/*TODO: Same as on the first statment on the other side of the `ifdef */
+					VALID_INSTRUCTION <= 0;
+				end else if(FIFO_SIZE>`L1_CACHE_SIZE'd3)begin
 					VALID_INSTRUCTION <= 1;
 					INSTRUCTION[31:24] <= INPUT_FIFO[FIFO_start];
 					INSTRUCTION[23:16] <= INPUT_FIFO[FIFO_start+`L1_CACHE_SIZE'd1];
@@ -189,15 +204,21 @@ always @(posedge clock) begin
 				if(INSTRUCTION_ADDRESS[0:0]==0 && FIFO_SIZE<{{(`L1_CACHE_SIZE-1){1'b1}},1'b0})begin
 					INPUT_FIFO[FIFO_end] <= external_data_bus[7:0];
 					INPUT_FIFO[FIFO_end+`L1_CACHE_SIZE'd1] <= external_data_bus[15:8];
-					FIFO_end <= FIFO_end+`L1_CACHE_SIZE'd2;
+					/* verilator lint_off BLKSEQ */
+					FIFO_end = FIFO_end+`L1_CACHE_SIZE'd2;
+					/* verilator lint_on BLKSEQ */
 					INSTRUCTION_ADDRESS <= INSTRUCTION_ADDRESS+20'd2;
 				end else if(INSTRUCTION_ADDRESS[0:0]==0)begin
 					INPUT_FIFO[FIFO_end] <= external_data_bus[7:0];
-					FIFO_end <= FIFO_end+`L1_CACHE_SIZE'd1;
+					/* verilator lint_off BLKSEQ */
+					FIFO_end = FIFO_end+`L1_CACHE_SIZE'd1;
+					/* verilator lint_on BLKSEQ */
 					INSTRUCTION_ADDRESS <= INSTRUCTION_ADDRESS+20'd1;
 				end else begin
 					INPUT_FIFO[FIFO_end] <= external_data_bus[15:8];
-					FIFO_end <= FIFO_end+`L1_CACHE_SIZE'd1;
+					/* verilator lint_off BLKSEQ */
+					FIFO_end = FIFO_end+`L1_CACHE_SIZE'd1;
+					/* verilator lint_on BLKSEQ */
 					INSTRUCTION_ADDRESS <= INSTRUCTION_ADDRESS+20'd1;
 				end
 				biu_state <= `BIU_NEXT_ACTION;
@@ -303,8 +324,8 @@ always @(posedge clock) begin
 			`BIU_RESET: begin
 				/* verilator lint_off BLKSEQ */
 				FIFO_start = `L1_CACHE_SIZE'b0;
+				FIFO_end = `L1_CACHE_SIZE'b0;
 				/* verilator lint_on BLKSEQ */
-				FIFO_end <= `L1_CACHE_SIZE'b0;
 				biu_state <= `BIU_NEXT_ACTION;
 				INSTRUCTION_ADDRESS <= 20'h0FFF0;
 				INSTRUCTION_LOCATION <= 16'hFFF0;