diff --git a/system/decoder.v b/system/decoder.v index 9640ad2..8ac7567 100644 --- a/system/decoder.v +++ b/system/decoder.v @@ -44,8 +44,8 @@ endmodule module decoder( input wire [15:0] CIR,input wire [15:0] FLAGS, output wire [4:0] INSTRUCTION_INFO, output wire [1:0]DECODER_SIGNALS,output reg [`PROC_STATE_BITS-1:0]next_state - ,output reg [1:0]MOD, output reg [2:0]RM, output reg [15:0] PARAM1,output reg [15:0] PARAM2 - ,output reg [1:0]in_alu1_sel1,output reg [1:0]in_alu1_sel2,output reg [2:0]out_alu1_sel + ,output reg [2:0]IN_MOD, output reg [2:0]RM, output reg [15:0] PARAM1,output reg [15:0] PARAM2 + ,output reg [1:0]in_alu1_sel1,output reg [1:0]in_alu1_sel2,output reg [2:0]OUT_MOD ,output wire [11:0]REGISTER_FILE_CONTROL ,output reg [2:0]ALU_1OP ,output reg [`UCODE_ADDR_BITS-1:0] seq_addr_entry, input wire SIMPLE_MICRO, input wire [`UCODE_ADDR_BITS-1:0] seq_addr_input @@ -71,7 +71,7 @@ microcode ucode(seq_addr_input,ucode_data); /* 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 */ -`define invalid_instruction next_state=`PROC_IF_STATE_ENTRY;ERROR=1;MOD=2'b11; +`define invalid_instruction next_state=`PROC_IF_STATE_ENTRY;ERROR=1;IN_MOD=2'b11; `define start_aligning_instruction unaligning=0; `define start_unaligning_instruction unaligning=1; @@ -91,10 +91,10 @@ always @( CIR or SIMPLE_MICRO or seq_addr_input ) begin `start_unaligning_instruction else `start_aligning_instruction - MOD=2'b11; + IN_MOD=2'b11; in_alu1_sel1=2'b00; in_alu1_sel2=2'b01; - out_alu1_sel=3'b011; + OUT_MOD=3'b011; reg_read_port2_addr={Wbit,3'b000}; reg_write_addr={Wbit,3'b000}; ALU_1OP=`ALU_OP_ADD; @@ -114,10 +114,10 @@ always @( CIR or SIMPLE_MICRO or seq_addr_input ) begin has_operands=1; Wbit=CIR[8:8]; Sbit=CIR[9:9]; - MOD=2'b11; + IN_MOD=2'b11; in_alu1_sel1=2'b00; in_alu1_sel2=2'b01; - out_alu1_sel={1'b0,MOD}; + OUT_MOD={1'b0,IN_MOD}; reg_read_port2_addr={Wbit,RM}; reg_write_addr={Wbit,RM}; ALU_1OP=`ALU_OP_ADD; @@ -136,18 +136,18 @@ always @( CIR or SIMPLE_MICRO or seq_addr_input ) begin has_operands=1; Wbit=CIR[8:8]; Sbit=CIR[9:9]; - MOD=CIR[7:6]; + IN_MOD=CIR[7:6]; RM=CIR[2:0]; if(((Wbit==1)&&(Sbit==1))||Wbit==0)begin `start_unaligning_instruction end else begin `invalid_instruction; end - if(MOD==2'b11)begin + if(IN_MOD==2'b11)begin in_alu1_sel1=2'b00; in_alu1_sel2=2'b01; reg_read_port2_addr={Wbit,RM}; - out_alu1_sel=3'b100; + OUT_MOD=3'b100; ALU_1OP=`ALU_OP_SUB; next_state=`PROC_DE_LOAD_8_PARAM; end else begin @@ -162,10 +162,10 @@ always @( CIR or SIMPLE_MICRO or seq_addr_input ) begin has_operands=1; Wbit=CIR[11:11]; /* IS 0 */ opcode_size=0; - MOD=2'b11; + IN_MOD=2'b11; in_alu1_sel1=2'b00; in_alu1_sel2=2'b00; - out_alu1_sel=3'b011; + OUT_MOD=3'b011; reg_write_addr={1'b0,CIR[10:8]}; PARAM1[7:0]=CIR[7:0]; PARAM2=0; @@ -179,10 +179,10 @@ always @( CIR or SIMPLE_MICRO or seq_addr_input ) begin has_operands=1; Wbit=CIR[11:11]; /*IS 1 */ opcode_size=0; - MOD=2'b11; + IN_MOD=2'b11; in_alu1_sel1=2'b00; in_alu1_sel2=2'b00; - out_alu1_sel=3'b011; + OUT_MOD=3'b011; reg_write_addr={1'b1,CIR[10:8]}; ALU_1OP=`ALU_OP_ADD; PARAM2=0; @@ -196,13 +196,13 @@ always @( CIR or SIMPLE_MICRO or seq_addr_input ) begin has_operands=0; `start_aligning_instruction opcode_size=1; - MOD=CIR[7:6]; + IN_MOD=CIR[7:6]; RM=CIR[2:0]; Wbit=CIR[8:8]; in_alu1_sel2=2'b00; if(CIR[9:9] == 1)begin /* Mem/Reg to reg */ - if(MOD==2'b11)begin + if(IN_MOD==2'b11)begin /*Reg to Reg*/ in_alu1_sel1=2'b01; reg_read_port1_addr={Wbit,RM}; @@ -212,21 +212,21 @@ always @( CIR or SIMPLE_MICRO or seq_addr_input ) begin in_alu1_sel1=2'b00; next_state=`RPOC_MEMIO_READ; end - out_alu1_sel=3'b011; + OUT_MOD=3'b011; reg_write_addr={Wbit,CIR[5:3]}; end else begin /* Reg to Mem/Reg */ - if(MOD==2'b11)begin + if(IN_MOD==2'b11)begin /*Reg to Reg*/ in_alu1_sel1=2'b01; - out_alu1_sel=3'b011; + OUT_MOD=3'b011; reg_write_addr={Wbit,RM}; next_state=`PROC_EX_STATE_ENTRY; end else begin /*Reg to Mem*/ in_alu1_sel1=2'b00; reg_read_port1_addr={Wbit,CIR[5:3]}; - out_alu1_sel={1'b0,MOD}; + OUT_MOD={1'b0,IN_MOD}; next_state=`PROC_DE_LOAD_REG_TO_PARAM; end reg_read_port1_addr={Wbit,CIR[5:3]}; @@ -247,8 +247,8 @@ always @( CIR or SIMPLE_MICRO or seq_addr_input ) begin Wbit=1; in_alu1_sel1=2'b01; in_alu1_sel2=2'b00; - out_alu1_sel=3'b011; - MOD=2'b11; + OUT_MOD=3'b011; + IN_MOD=2'b11; PARAM2=1; reg_read_port1_addr={1'b1,CIR[10:8]}; reg_write_addr={1'b1,CIR[10:8]}; @@ -268,19 +268,19 @@ always @( CIR or SIMPLE_MICRO or seq_addr_input ) begin opcode_size=1; `start_aligning_instruction Wbit=CIR[8:8]; - MOD=CIR[7:6]; + IN_MOD=CIR[7:6]; RM=CIR[2:0]; - in_alu1_sel1=(MOD==2'b11)? 2'b01 : 2'b00; + in_alu1_sel1=(IN_MOD==2'b11)? 2'b01 : 2'b00; in_alu1_sel2=2'b00;/* number 1 */ PARAM2=1; - out_alu1_sel={1'b0,MOD}; + OUT_MOD={1'b0,IN_MOD}; - /*in case MOD=11 */ + /*in case IN_MOD=11 */ reg_read_port1_addr={1'b0,RM}; reg_write_addr={1'b0,RM}; ALU_1OP=(CIR[3:3]==1)?`ALU_OP_SUB:`ALU_OP_ADD; - if ( MOD == 2'b11 ) + if ( IN_MOD == 2'b11 ) next_state=`PROC_EX_STATE_ENTRY; else next_state=`RPOC_MEMIO_READ; @@ -292,7 +292,7 @@ always @( CIR or SIMPLE_MICRO or seq_addr_input ) begin has_operands=0; opcode_size=0; `start_unaligning_instruction - MOD=2'b11; + IN_MOD=2'b11; HALT=1; next_state=`PROC_HALT_STATE; end @@ -310,11 +310,11 @@ always @( CIR or SIMPLE_MICRO or seq_addr_input ) begin `start_unaligning_instruction else `start_aligning_instruction - MOD=2'b11; + IN_MOD=2'b11; in_alu1_sel1=2'b00; in_alu1_sel2=2'b01; reg_read_port2_addr={Wbit,3'b000}; - out_alu1_sel=3'b100; + OUT_MOD=3'b100; ALU_1OP=`ALU_OP_SUB; if(Wbit==1) next_state=`PROC_DE_LOAD_16_PARAM; @@ -341,7 +341,7 @@ always @( CIR or SIMPLE_MICRO or seq_addr_input ) begin in_alu1_sel2=2'b00; PARAM2={{8{CIR[7:7]}},CIR[7:0]}; ALU_1OP=`ALU_OP_ADD_SIGNED_B; - out_alu1_sel=3'b101; + OUT_MOD=3'b101; case(CIR[11:9]) 3'b000: begin /* Jump on (not) Overflow */ @@ -389,7 +389,7 @@ always @( CIR or SIMPLE_MICRO or seq_addr_input ) begin in_alu1_sel2=2'b00; PARAM2={{8{CIR[7:7]}},CIR[7:0]}; ALU_1OP=`ALU_OP_ADD_SIGNED_B; - out_alu1_sel=3'b101; + OUT_MOD=3'b101; next_state=`PROC_EX_STATE_ENTRY; end 11'b1100_1101_xxx:begin @@ -418,6 +418,24 @@ always @( CIR or SIMPLE_MICRO or seq_addr_input ) begin PARAM2=2; //substract from sp seq_addr_entry=`UCODE_CALL_ENTRY; end + 11'b11000011_xxx:begin + /* RET - Return from call within segment */ + /* | 1 1 0 0 0 0 1 1 | */ + + // Microcode instruction + `start_unaligning_instruction + opcode_size=0; + /* TODO: This is a hack to prevent IF from + * thinking it can retrieve half of the opcode + * from CIR and the previous byte on the data + * bus. We are jumping so all that data has to + * be thrown away */ + has_operands=1; + Wbit=1; + Sbit=0; + PARAM2=2; + seq_addr_entry=`UCODE_RET_ENTRY; + end default:begin `invalid_instruction end @@ -431,12 +449,12 @@ always @( CIR or SIMPLE_MICRO or seq_addr_input ) begin 2'b00: next_state=`PROC_EX_STATE_ENTRY; 2'b01: next_state=`PROC_DE_LOAD_16_PARAM; 2'b10: next_state=`PROC_DE_LOAD_8_PARAM; - 2'b11: next_state=`PROC_DE_LOAD_REG_TO_PARAM; + 2'b11: next_state=`RPOC_MEMIO_READ; endcase reg_write_addr=ucode_data[11:8 ]; in_alu1_sel1 =ucode_data[13:12]; in_alu1_sel2 =ucode_data[15:14]; - out_alu1_sel =ucode_data[18:16]; + OUT_MOD =ucode_data[18:16]; /*1:1 map essentially but I want to keep the spec for these bits seperate * from the alu op select bits*/ case(ucode_data[21:19]) @@ -448,6 +466,7 @@ always @( CIR or SIMPLE_MICRO or seq_addr_input ) begin 3'b101: ALU_1OP=`ALU_OP_ADD_SIGNED_B; endcase reg_read_port1_addr=ucode_data[25:22]; + IN_MOD =ucode_data[28:26]; end end diff --git a/system/processor.v b/system/processor.v index f3ad4e8..3af933f 100644 --- a/system/processor.v +++ b/system/processor.v @@ -35,7 +35,6 @@ reg [`PROC_STATE_BITS-1:0] state; /*############ Decoder ########################################################## */ wire Wbit, Sbit, unaligning_instruction,opcode_size, has_operands; wire [`PROC_STATE_BITS-1:0] next_state; -wire [1:0]MOD; wire [2:0]RM; wire [15:0]DE_PARAM1;// Input param1 form decoder to alu wire [15:0]DE_PARAM2; @@ -50,8 +49,8 @@ reg SIMPLE_MICRO; /* otuput simple decodings (=0) or microcode data (=1) */ decoder decoder( CIR,FLAGS,INSTRUCTION_INFO,DECODER_SIGNALS,next_state - ,MOD,RM,DE_PARAM1,DE_PARAM2 - ,in_alu1_sel1,in_alu1_sel2,out_alu1_sel + ,IN_MOD,RM,DE_PARAM1,DE_PARAM2 + ,in_alu1_sel1,in_alu1_sel2,OUT_MOD ,DE_REGISTER_CONTROL ,ALU_1OP ,ucode_seq_addr_entry,SIMPLE_MICRO,ucode_seq_addr @@ -108,8 +107,9 @@ register_file register_file(reg_write_addr,reg_write_data,reg_write_we,reg_read_ // ALU 1 reg [1:0] in_alu1_sel1; reg [1:0] in_alu1_sel2; -/* out_alu1_sel : { EXTRA_FUNCTIONS_BIT[0:0], MOD_OR_EXTRA_FUNCTION[1:0] } */ -reg [2:0] out_alu1_sel; +/* OUT_MOD : { EXTRA_FUNCTIONS_BIT[0:0], MOD_OR_EXTRA_FUNCTION[1:0] } */ +reg [2:0] IN_MOD; +reg [2:0] OUT_MOD; mux4 #(.WIDTH(16)) MUX16_1A( PARAM1, @@ -123,7 +123,7 @@ mux4 #(.WIDTH(16)) MUX16_1B( PARAM2, reg_read_port2_data, {ProgCount[14:0],unaligned_access^unaligning_instruction}, - 16'b0000000000000001, /*1 Constant*/ + 16'b0000000000000000, /*0 Constant*/ in_alu1_sel2, ALU_1B); @@ -185,7 +185,7 @@ always @(negedge clock) begin * be done by decode at the end*/ if (ucode_seq_addr==`UCODE_NO_INSTRUCTION) unaligned_access=unaligning_instruction^unaligned_access; - case(out_alu1_sel) /*TODO: use RM*/ + case(OUT_MOD) /*TODO: use RM*/ 3'b000, 3'b001, 3'b010 : begin @@ -241,8 +241,6 @@ always @(negedge clock) begin state=`PROC_NEXT_MICROCODE; end 3'b101:begin /* Program Counter*/ - //if(SIMPLE_MICRO==1) - // ERROR=1; ProgCount={5'b00000,ALU_1O[15:1]}; unaligned_access=ALU_1O[0:0]; we_jumped=1; @@ -431,47 +429,60 @@ always @(posedge clock) begin end `RPOC_MEMIO_READ:begin /*Decode MOD R/M, read the data and place it to PARAM1*/ - case (RM) - 3'b000:begin - /*[BX]+[SI]*/ - `invalid_instruction + case (IN_MOD) + 3'b000, + 3'b001, + 3'b010:begin + case (RM) + 3'b000:begin + /*[BX]+[SI]*/ + `invalid_instruction + end + 3'b001:begin + /*[BX]+[SI]*/ + `invalid_instruction + end + 3'b010:begin + /*[BP]+[SI]*/ + `invalid_instruction + end + 3'b011:begin + /*[BP]+[DI]*/ + `invalid_instruction + end + 3'b100:begin + /*[SI]*/ + reg_read_port1_addr=4'b1110; + state=`PROC_MEMIO_READ_SETADDR; + end + 3'b101:begin + /*[DI]*/ + reg_read_port1_addr=4'b1111; + state=`PROC_MEMIO_READ_SETADDR; + end + 3'b110:begin + /*d16 */ + `invalid_instruction + end + 3'b111:begin + /*[BX]*/ + reg_read_port1_addr=4'b1011; + state=`PROC_MEMIO_READ_SETADDR; + end + endcase + if(IN_MOD!=3'b000)begin + /*Actually check if 01 and add the 8bits or if 10 add the 16bits ....*/ + `invalid_instruction; + end end - 3'b001:begin - /*[BX]+[SI]*/ - `invalid_instruction - end - 3'b010:begin - /*[BP]+[SI]*/ - `invalid_instruction - end - 3'b011:begin - /*[BP]+[DI]*/ - `invalid_instruction - end - 3'b100:begin - /*[SI]*/ - reg_read_port1_addr=4'b1110; + 3'b110:begin /* Indirect write on SP */ + reg_read_port1_addr=4'b1100; state=`PROC_MEMIO_READ_SETADDR; end - 3'b101:begin - /*[DI]*/ - reg_read_port1_addr=4'b1111; - state=`PROC_MEMIO_READ_SETADDR; - end - 3'b110:begin - /*d16 */ + default:begin `invalid_instruction end - 3'b111:begin - /*[BX]*/ - reg_read_port1_addr=4'b1011; - state=`PROC_MEMIO_READ_SETADDR; - end endcase - if(MOD!=2'b00)begin - /*Actually check if 01 and add the 8bits or if 10 add the 16bits ....*/ - `invalid_instruction; - end end `PROC_MEMIO_GET_ALIGNED_DATA:begin diff --git a/system/ucode.txt b/system/ucode.txt index a530d21..aa80c60 100644 --- a/system/ucode.txt +++ b/system/ucode.txt @@ -17,6 +17,10 @@ You should have received a copy of the GNU General Public License along with this program. If not, see . */ +//imd: IN_MOD +// +//rr1: reg_read_port1_addr +// //a1f: ALU 1 operation (function) // 000:ALU_OP_ADD // 001:ALU_OP_SUB @@ -25,7 +29,7 @@ // 100:ALU_OP_XOR // 101:ALU_OP_ADD_SIGNED_B // -//a1o: out_alu1_sel. Handled in `PROC_EX_STATE_EXIT +//a1o: OUT_MOD. Handled in `PROC_EX_STATE_EXIT // //a12: In ALU 1 sel 2 // @@ -37,14 +41,18 @@ // 00: PROC_EX_STATE_ENTRY // 01: PROC_DE_LOAD_16_PARAM // 10: PROC_DE_LOAD_8_PARAM -// 11: PROC_DE_LOAD_REG_TO_PARAM +// 11: RPOC_MEMIO_READ // //Nxt M: Next microcode address - -// 24 21 18 15 13 11 7 5 0 -// rr1 |a1f|a1o|a12|a11|rwa |nxs|Nxt M | @000 0000_000_000__00__00_0000__00_000000 -@001 zzzz_000_110__10__11_0111__01_000010 // ALU_1: 0 ALU_2: PC ALU_OP:ADD ALU_out: [SP] (also fetch the opcode argument to PARAM1) -@002 1100_001_011__00__01_1100__00_000011 // ALU_1: SP ALU_2: PARAM2 (2) ALU_OP:SUB ALU_out: SP -@003 zzzz_000_101__10__00_zzzz__00_000000 // ALU_1: PARAM1 (arg) ALU_2: PC ALU_OP:ADD ALU_out: PC + +// 28 25 21 18 15 13 11 7 5 0 +// imd|rr1 |a1f|a1o|a12|a11|rwa |nxs|Nxt M | +@001 011_1100_001_011__00__01_1100__01_000010 // ALU_1: SP ALU_2: PARAM2 (2) ALU_OP:SUB ALU_out: SP (also fetch the opcode argument to PARAM1) +@002 011_zzzz_000_110__10__11_zzzz__00_000011 // ALU_1: 0 ALU_2: PC ALU_OP:ADD ALU_out: [SP] +@003 011_zzzz_000_101__10__00_zzzz__00_000000 // ALU_1: PARAM1 (arg) ALU_2: PC ALU_OP:ADD ALU_out: PC + +// imd|rr1 |a1f|a1o|a12|a11|rwa |nxs|Nxt M | +@004 110_zzzz_000_101__11__00_zzzz__11_000101 // ALU_1: PARAM1 ([SP]) ALU_2: 0 ALU_OP:ADD ALU_out: PC +@005 011_1100_000_011__00__01_1100__00_000000 // ALU_1: SP ALU_2: PARAM2 (2) ALU_OP:ADD ALU_out: SP diff --git a/system/ucode_header.v b/system/ucode_header.v index d36a08f..1a53528 100644 --- a/system/ucode_header.v +++ b/system/ucode_header.v @@ -19,8 +19,9 @@ `define UCODE_ADDR_BITS 5 `define UCODE_DATA_BITS 32 -`define UCODE_SIZE 4 +`define UCODE_SIZE 6 /* DEFINE ADDRESSES IN THE MICROCODE */ `define UCODE_NO_INSTRUCTION 5'b00000 `define UCODE_CALL_ENTRY 5'b00001 +`define UCODE_RET_ENTRY 5'b00100