From c3a2f5eb01c45d359b5b9654d23ae04b97499fd3 Mon Sep 17 00:00:00 2001 From: "(Tim) Efthimis Kritikos" Date: Thu, 9 Feb 2023 14:46:21 +0000 Subject: [PATCH] Added primitive decode stage, improved state handling and fixed CIR register --- cpu/gtkwave_savefile.gtkw | 26 +++++---- cpu/proc_state_def.v | 12 ++++ cpu/processor.v | 115 +++++++++++++++++++++++++++----------- cpu/testbench.v | 6 +- 4 files changed, 112 insertions(+), 47 deletions(-) create mode 100644 cpu/proc_state_def.v diff --git a/cpu/gtkwave_savefile.gtkw b/cpu/gtkwave_savefile.gtkw index 9b2c765..00d6bbe 100644 --- a/cpu/gtkwave_savefile.gtkw +++ b/cpu/gtkwave_savefile.gtkw @@ -1,32 +1,34 @@ [*] [*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI -[*] Wed Feb 8 23:43:14 2023 +[*] Thu Feb 9 14:44:08 2023 [*] [dumpfile] "/home/user/UNI_DATA/COMS30046_2022_TB-2/projects/9086/cpu/test.lx2" -[dumpfile_mtime] "Wed Feb 8 23:42:51 2023" -[dumpfile_size] 470 +[dumpfile_mtime] "Thu Feb 9 14:43:59 2023" +[dumpfile_size] 757 [savefile] "/home/user/UNI_DATA/COMS30046_2022_TB-2/projects/9086/cpu/gtkwave_savefile.gtkw" [timestart] 0 -[size] 1534 1059 +[size] 1630 1059 [pos] -1 -1 -*-20.795050 2883000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +*-22.795050 2010000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 [treeopen] tb. [sst_width] 221 [signals_width] 293 [sst_expanded] 1 [sst_vpaned_height] 313 -@28 -tb.p.clock[0] -tb.p.reset[0] -tb.p.start[0] @29 -tb.p.state[2:0] +tb.p.clock[0] @28 -tb.p.instruction_finished[0] +tb.p.reset[0] @22 +tb.p.state[3:0] tb.p.external_address_bus[19:0] tb.p.external_data_bus[15:0] +tb.p.CIR[15:0] @28 -tb.p.read[0] +tb.p.EXCEPTION[0] +tb.p.ADD_INST[0] +tb.p.INC_INST[0] +@22 +tb.p.PARAM1[15:0] [pattern_trace] 1 [pattern_trace] 0 diff --git a/cpu/proc_state_def.v b/cpu/proc_state_def.v new file mode 100644 index 0000000..ae01d09 --- /dev/null +++ b/cpu/proc_state_def.v @@ -0,0 +1,12 @@ +`define PROC_HALT_STATE 4'b0000 + +/*INSTRUCTION FETCH STATE*/ +`define PROC_IF_STATE_ENTRY 4'b0001 +`define PROC_IF_WRITE_CIR 4'b0010 + +/*DECODE SATE*/ +`define PROC_DE_STATE_ENTRY 4'b0100 +`define PROC_DE_LOAD_16_PARAM 4'b0101 + +/*EXECUTE STATE*/ +`define PROC_EX_STATE_ENTRY 4'b1000 diff --git a/cpu/processor.v b/cpu/processor.v index f6ef2dd..f4562e5 100644 --- a/cpu/processor.v +++ b/cpu/processor.v @@ -1,4 +1,5 @@ `timescale 1ns/1ps +`include "proc_state_def.v" module clock_gen (input enable, output reg clk); @@ -52,53 +53,103 @@ end endmodule -module processor ( input clock, input reset , output reg [19:0] external_address_bus, inout [15:0] external_data_bus,output reg read, output reg write); +module processor ( input clock, input reset , output reg [19:0] external_address_bus, inout [15:0] external_data_bus,output reg read, output reg write, output reg HALT); /* State */ -reg [2:0] state; -reg start=0; +reg [3:0] state; reg instruction_finished; /* Registers */ reg [19:0] ProgCount; -reg [14:0] CIR; +reg [15:0] CIR; +reg [15:0] PARAM1; +reg [15:0] PARAM2; /* RESET LOGIC */ always @(negedge reset) begin if (reset==0) begin @(posedge clock); - state=0; ProgCount=0;//TODO: Reset Vector - #10 - start=1; + ADD_INST=0; + EXCEPTION=0; + INC_INST=0; + HALT=0; + @(negedge clock); + @(posedge clock); + state=`PROC_IF_STATE_ENTRY; end end -/* CLOCK LOGIC */ -always @(posedge clock) begin - if(instruction_finished) - state =0; - else - if (clock && start==1) - state=state+1; -end - -always @(state) begin - if (state==5) - instruction_finished=1; - else - instruction_finished=0; -end - /* Processor stages */ -always @(state) begin - if (state=='b000) begin - external_address_bus <= ProgCount; - read <= 0; - write <= 1; - end else if ( state=='b001 ) begin - CIR <= external_data_bus; - ProgCount=ProgCount+1; - end +reg ADD_INST,EXCEPTION,INC_INST; + +always @(negedge clock) begin + case(state) + `PROC_IF_WRITE_CIR:begin + CIR <= external_data_bus; + ProgCount=ProgCount+1; + state=`PROC_DE_STATE_ENTRY; + end + endcase +end + +always @(posedge clock) begin + case(state) + `PROC_HALT_STATE: + HALT=1; + `PROC_IF_STATE_ENTRY:begin + external_address_bus <= ProgCount; + read <= 0; + write <= 1; + state=`PROC_IF_WRITE_CIR; + end + `PROC_DE_STATE_ENTRY:begin + external_address_bus <= ProgCount; /*Remenance from IF*/ + case(CIR[15:10]) + 6'b100000 : begin + case (CIR[5:3]) + 3'b000 :begin + ADD_INST=1; + state=`PROC_DE_LOAD_16_PARAM; + end + default:begin + EXCEPTION=1; + state=`PROC_EX_STATE_ENTRY; + end + endcase + end + 6'b111111 : begin + if (CIR[9:9] == 1 ) begin + case (CIR[5:3]) + 3'b000 :begin + INC_INST=1; + state=`PROC_EX_STATE_ENTRY; + end + default:begin + EXCEPTION=1; + state=`PROC_EX_STATE_ENTRY; + end + endcase + end else begin + EXCEPTION=1; + state=`PROC_EX_STATE_ENTRY; + end + end + default:begin + EXCEPTION=1; + state=`PROC_EX_STATE_ENTRY; + end + endcase + end + `PROC_DE_LOAD_16_PARAM:begin + PARAM1 <= external_data_bus; + ProgCount=ProgCount+1; + state=`PROC_EX_STATE_ENTRY; + end + `PROC_EX_STATE_ENTRY:begin + EXCEPTION=0;ADD_INST=0;INC_INST=0; + state=`PROC_IF_STATE_ENTRY; + end + endcase end endmodule diff --git a/cpu/testbench.v b/cpu/testbench.v index c680966..553e308 100644 --- a/cpu/testbench.v +++ b/cpu/testbench.v @@ -4,9 +4,9 @@ reg reset; reg clk_enable; wire [19:0]address_bus; wire [15:0]data_bus; -wire rd,wr,romcs; +wire rd,wr,romcs,HALT; -processor p(clock,reset,address_bus,data_bus,rd,wr); +processor p(clock,reset,address_bus,data_bus,rd,wr,HALT); rom bootrom(address_bus,data_bus,rd,romcs); `define CPU_SPEED 1000 @@ -22,7 +22,7 @@ initial begin #($random%500) reset = 0; - #(100) + #(`CPU_SPEED) reset = 1; #(`CPU_SPEED*30)