From b1108e375d686bf6daca81466031fedc30effd1c Mon Sep 17 00:00:00 2001
From: "(Tim) Efthimis Kritikos" <efkf@firemail.cc>
Date: Wed, 6 Dec 2023 18:12:57 +0000
Subject: [PATCH] Build system: Fixed standalone ./system/Makefile build and
 general Makefile improvements

---
 system/Makefile                                | 12 ++++++------
 system/fpga_config/OrangeCrab_r0.2.1/config.mk |  4 ++--
 2 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/system/Makefile b/system/Makefile
index f6aeded..009492a 100644
--- a/system/Makefile
+++ b/system/Makefile
@@ -15,12 +15,14 @@
 #   You should have received a copy of the GNU General Public License
 #   along with this program.  If not, see <http://www.gnu.org/licenses/>.
 #
-
 SOURCES=processor.v memory.v registers.v alu.v decoder.v general.v biu.v execute.v
 INCLUDES=exec_state_def.v alu_header.v config.v ucode_header.v error_header.v
-BOOT_CODE=boot_code.txt
 MICROCODE=ucode.txt
+SYSTEM_VVP=system.vvp
+PRINT_PATH_PREFIX=./
 
+BOOT_CODE=boot_code.txt
+VERILATOR_BIN=obj_dir/Vsystem
 NO_ASM=0
 include ../common.mk
 
@@ -32,8 +34,6 @@ EVENT_SIM_TESTBENCH=testbench.v
 VERILATOR_TESTBENCH=testbench.cpp
 SIMULATION_TOP_LEVEL_SOURCE=system.v
 GTKWSAVE=../gtkwave_savefile.gtkw
-VERILATOR_BIN=obj_dir/Vsystem
-SYSTEM_VVP=system.vvp
 
 #build options
 VERILATOR_OPTS += --cc --exe
@@ -55,7 +55,7 @@ ${SYSTEM_VVP} : ${SIMULATION_TOP_LEVEL_SOURCE} ${SOURCES} ${INCLUDES} ${EVENT_SI
 	${Q}iverilog -g2012 -D CALCULATE_IPC -D OUTPUT_JSON_STATISTICS -o "$@" ${SIMULATION_TOP_LEVEL_SOURCE} ${SOURCES} ${EVENT_SIM_TESTBENCH}
 
 ${VERILATOR_BIN}: ${VERILATOR_BIN}.mk
-	${Q}make ${MAKEOPTS} OPT_FAST="-O2 -march=native -mtune=native" -C obj_dir -f ../verilator_makefile Vsystem
+	${Q}make ${MAKEOPTS} PRINT_PATH_PREFIX=${PRINT_PATH_PREFIX}obj_dir/ OPT_FAST="-O2 -march=native -mtune=native" -C obj_dir -f ../verilator_makefile Vsystem
 
 ${VERILATOR_BIN}.mk: ${VERILATOR_TESTBENCH} ${SIMULATION_TOP_LEVEL_SOURCE} ${SOURCES} ${INCLUDES}
 	${QUIET_VERILATOR}
@@ -106,7 +106,7 @@ ${BUILD_FILES_PREFIX}synth_ecp5_${FPGA_BOARD}.json: ${SYNTHESIS_SOURCES} ${FPGA_
 ##########################################
 ##     PLACE AND ROUTE RECIPES
 
-${BUILD_FILES_PREFIX}nextpnr_${BUILD_NAME}.bit:${BUILD_FILES_PREFIX}synth_${FPGA_BOARD}.json
+${BUILD_FILES_PREFIX}nextpnr-ecp5_${BUILD_NAME}.bit:${BUILD_FILES_PREFIX}synth_${FPGA_BOARD}.json
 	${QUIET_NEXTPNR}
 	${Q}printf '\e[1;30mNotice: nextpnr rng seed is : %s\e[0m\n' "${FPGA_SEED}"
 	${Q} nextpnr-ecp5 --seed ${FPGA_SEED} --Werror -q --json $< --textcfg "$@_config_temp" ${NEXTPNR_ECP5_DEV} --package ${ECP5_PACKAGE} --speed ${ECP5_SPEED_GRADE} --lpf fpga_config/${FPGA_BOARD}/pin_constraint.pcf --report=${BUILD_FILES_PREFIX}nextpnr_report_${BUILD_NAME}.json
diff --git a/system/fpga_config/OrangeCrab_r0.2.1/config.mk b/system/fpga_config/OrangeCrab_r0.2.1/config.mk
index 2868967..cd0a49d 100644
--- a/system/fpga_config/OrangeCrab_r0.2.1/config.mk
+++ b/system/fpga_config/OrangeCrab_r0.2.1/config.mk
@@ -16,7 +16,7 @@ FPGA_FILE_EXT=dfu
 ECP5_SPEED_GRADE=8
 
 
-########   End fo user configuration   ########
+########   End of user configuration   ########
 
 SOC_SYNTHESIS_SOURCES=peripherals/I2C_driver.v peripherals/ascii_to_HD44780_driver.v peripherals/pcf8574_for_HD44780.v peripherals/Wishbone_IO_driver.v peripherals/Wishbone_memory_driver.v external_ip/litedram_core_ecp5_phy.v
 
@@ -24,7 +24,7 @@ FPGA_BOOTCODE=../boot_code/bios.stxt
 
 upload: dfu_upload
 
-${BUILD_FILES_PREFIX}bitstream_${BUILD_NAME}.bit:${BUILD_FILES_PREFIX}nextpnr_${BUILD_NAME}.bit
+${BUILD_FILES_PREFIX}bitstream_${BUILD_NAME}.bit:${BUILD_FILES_PREFIX}nextpnr-ecp5_${BUILD_NAME}.bit
 	${Q}cp "$^" "$@"
 
 ${BUILD_FILES_PREFIX}synth_${FPGA_BOARD}.json:${BUILD_FILES_PREFIX}synth_ecp5_${FPGA_BOARD}.json