diff --git a/system/biu.v b/system/biu.v
index 71b1267..1ff2d30 100644
--- a/system/biu.v
+++ b/system/biu.v
@@ -101,14 +101,10 @@ always @(posedge clock) begin
 		write <= 1;
 		sane <= 0;
 		biu_state <= `BIU_RESET1;
-		/* verilator lint_off BLKSEQ */
-		FIFO_start = `L1_CACHE_SIZE'b0;
-		FIFO_end = `L1_CACHE_SIZE'b0;
-		/* verilator lint_on BLKSEQ */
+		FIFO_start <= `L1_CACHE_SIZE'b0;
+		FIFO_end <= `L1_CACHE_SIZE'b0;
 	end else if ( jump_req ) begin
-		/* verilator lint_off BLKSEQ */
-		FIFO_start = FIFO_end ;
-		/* verilator lint_on BLKSEQ */
+		FIFO_start <= FIFO_end ;
 		INSTRUCTION_ADDRESS <= { 4'b0 , ADDRESS_INPUT };
 		INSTRUCTION_LOCATION <= ADDRESS_INPUT;
 		func <= 1;
@@ -125,9 +121,7 @@ always @(posedge clock) begin
 					IOMEM <= MEM_OR_IO;
 					biu_state <= (Wbit==0) ? `BIU_PUT_BYTE : (ADDRESS_INPUT[0:0]?`BIU_PUT_UNALIGNED_16BIT_DATA:`BIU_PUT_ALIGNED_16BIT_DATA) ;
 					INSTRUCTION_ADDRESS <= {4'b0,INSTRUCTION_LOCATION} ;
-					/* verilator lint_off BLKSEQ */
-					FIFO_end=FIFO_start;
-					/* verilator lint_on BLKSEQ */
+					FIFO_end<=FIFO_start;
 				end else if ( read_request ) begin
 					func<=0;
 					DATA_ADDRESS <= { 4'b0 , ADDRESS_INPUT };
@@ -155,23 +149,17 @@ always @(posedge clock) begin
 			/*************** INSTRUCTION FIFO READ ***************/
 			`BIU_READ: begin
 				if(INSTRUCTION_ADDRESS[0:0]==0 && FIFO_SIZE<{{(`L1_CACHE_SIZE-1){1'b1}},1'b0})begin
-					/* verilator lint_off BLKSEQ */
-					INPUT_FIFO[FIFO_end] = external_data_bus_read[7:0];
-					INPUT_FIFO[FIFO_end+`L1_CACHE_SIZE'd1] = external_data_bus_read[15:8];
-					FIFO_end = FIFO_end+`L1_CACHE_SIZE'd2;
-					/* verilator lint_on BLKSEQ */
+					INPUT_FIFO[FIFO_end] <= external_data_bus_read[7:0];
+					INPUT_FIFO[FIFO_end+`L1_CACHE_SIZE'd1] <= external_data_bus_read[15:8];
+					FIFO_end <= FIFO_end+`L1_CACHE_SIZE'd2;
 					INSTRUCTION_ADDRESS <= INSTRUCTION_ADDRESS+20'd2;
 				end else if(INSTRUCTION_ADDRESS[0:0]==0)begin
-					/* verilator lint_off BLKSEQ */
-					INPUT_FIFO[FIFO_end] = external_data_bus_read[7:0];
-					FIFO_end = FIFO_end+`L1_CACHE_SIZE'd1;
-					/* verilator lint_on BLKSEQ */
+					INPUT_FIFO[FIFO_end] <= external_data_bus_read[7:0];
+					FIFO_end <= FIFO_end+`L1_CACHE_SIZE'd1;
 					INSTRUCTION_ADDRESS <= INSTRUCTION_ADDRESS+20'd1;
 				end else begin
-					/* verilator lint_off BLKSEQ */
-					INPUT_FIFO[FIFO_end] = external_data_bus_read[15:8];
-					FIFO_end = FIFO_end+`L1_CACHE_SIZE'd1;
-					/* verilator lint_on BLKSEQ */
+					INPUT_FIFO[FIFO_end] <= external_data_bus_read[15:8];
+					FIFO_end <= FIFO_end+`L1_CACHE_SIZE'd1;
 					INSTRUCTION_ADDRESS <= INSTRUCTION_ADDRESS+20'd1;
 				end
 				biu_state <= `BIU_NEXT_ACTION;
@@ -279,8 +267,8 @@ always @(posedge clock) begin
 			end
 			`BIU_RESET2: begin
 				/* verilator lint_off BLKSEQ */
-				FIFO_start = `L1_CACHE_SIZE'b0;
-				FIFO_end = `L1_CACHE_SIZE'b0;
+				FIFO_start <= `L1_CACHE_SIZE'b0;
+				FIFO_end <= `L1_CACHE_SIZE'b0;
 				/* verilator lint_on BLKSEQ */
 				biu_state <= `BIU_NEXT_ACTION;
 				INSTRUCTION_ADDRESS <= 20'h0FFF0;
@@ -293,34 +281,9 @@ always @(posedge clock) begin
 			end
 		endcase
 	end
-end
 
-wire [2:0] Isize;
-InstrSize InstrSize({INSTRUCTION[31:24],INSTRUCTION[21:19]},Isize);
+	/**** UPDATE VALID_INSTRUCTION ****/
 
-`ifdef INCLUDE_EARLY_CALC_CIRUIT
-wire [2:0] fifoIsize;
-wire Isit1;
-InstrSize fifoInstrSize({INPUT_FIFO[FIFO_start][7:0],INPUT_FIFO[FIFO_start+`L1_CACHE_SIZE'd1][5:3]},fifoIsize);
-Is1 Is1(INPUT_FIFO[FIFO_start][7:0],Isit1);
-`endif
-
-`ifdef DOUBLE_INSTRUCTION_LOAD
-wire [2:0] fifoIsize2;
-InstrSize fifoInstrSize2(
-	{ INPUT_FIFO[FIFO_start+{{`L1_CACHE_SIZE-3{1'b0}},fifoIsize}][7:0], INPUT_FIFO[FIFO_start+{{`L1_CACHE_SIZE-3{1'b0}},fifoIsize}+`L1_CACHE_SIZE'd1][5:3]}
-	,fifoIsize2
-	);
-`endif
-
-always @( valid_instruction_ack ) begin
-	/* verilator lint_off BLKSEQ */
-	FIFO_start = FIFO_start + {{`L1_CACHE_SIZE-3{1'b0}},Isize};
-	/* verilator lint_on BLKSEQ */
-	INSTRUCTION_LOCATION <= INSTRUCTION_LOCATION + {13'd0,Isize};
-end
-
-always @( FIFO_start or FIFO_end ) begin
 	if(jump_req==1)begin
 		VALID_INSTRUCTION <= 0;
 	end else if(sane==1) begin
@@ -396,4 +359,29 @@ always @( FIFO_start or FIFO_end ) begin
 	end
 end
 
+wire [2:0] Isize;
+InstrSize InstrSize({INSTRUCTION[31:24],INSTRUCTION[21:19]},Isize);
+
+`ifdef INCLUDE_EARLY_CALC_CIRUIT
+wire [2:0] fifoIsize;
+wire Isit1;
+InstrSize fifoInstrSize({INPUT_FIFO[FIFO_start][7:0],INPUT_FIFO[FIFO_start+`L1_CACHE_SIZE'd1][5:3]},fifoIsize);
+Is1 Is1(INPUT_FIFO[FIFO_start][7:0],Isit1);
+`endif
+
+`ifdef DOUBLE_INSTRUCTION_LOAD
+wire [2:0] fifoIsize2;
+InstrSize fifoInstrSize2(
+	{ INPUT_FIFO[FIFO_start+{{`L1_CACHE_SIZE-3{1'b0}},fifoIsize}][7:0], INPUT_FIFO[FIFO_start+{{`L1_CACHE_SIZE-3{1'b0}},fifoIsize}+`L1_CACHE_SIZE'd1][5:3]}
+	,fifoIsize2
+	);
+`endif
+
+always @( valid_instruction_ack ) begin
+	/* verilator lint_off BLKSEQ */
+	FIFO_start <= FIFO_start + {{`L1_CACHE_SIZE-3{1'b0}},Isize};
+	/* verilator lint_on BLKSEQ */
+	INSTRUCTION_LOCATION <= INSTRUCTION_LOCATION + {13'd0,Isize};
+end
+
 endmodule