From 694f708a322b4a712ed99545846d705d356fccc6 Mon Sep 17 00:00:00 2001
From: "(Tim) Efthimis Kritikos" <efkf@firemail.cc>
Date: Sat, 4 Nov 2023 06:59:46 +0000
Subject: [PATCH] Fixed some relatively low hanging fruit

---
 system/biu.v     | 25 ++++++++++---------------
 system/decoder.v |  8 +++++---
 2 files changed, 15 insertions(+), 18 deletions(-)

diff --git a/system/biu.v b/system/biu.v
index 5b4fafb..250b10d 100644
--- a/system/biu.v
+++ b/system/biu.v
@@ -89,19 +89,6 @@ wire [`L1_CACHE_SIZE-1:0] FIFO_SIZE = FIFO_end-FIFO_start;
 reg [3:0] biu_state;
 reg sane;
 
-always @(negedge reset) begin
-	biu_state <= `BIU_HALT;
-	write <= 1;
-	sane <= 0;
-end
-always @(posedge reset) begin
-	biu_state <= `BIU_RESET1;
-	/* verilator lint_off BLKSEQ */
-	FIFO_start = `L1_CACHE_SIZE'b0;
-	FIFO_end = `L1_CACHE_SIZE'b0;
-	/* verilator lint_on BLKSEQ */
-end
-
 reg jump_req_latch;
 
 reg func;
@@ -111,7 +98,16 @@ reg [19:0]DATA_ADDRESS;
 assign external_address_bus= func ? INSTRUCTION_ADDRESS : DATA_ADDRESS ;
 
 always @(posedge clock) begin
-	if ( jump_req_latch ) begin
+	if ( reset == 0 ) begin
+		biu_state <= `BIU_HALT;
+		write <= 1;
+		sane <= 0;
+		biu_state <= `BIU_RESET1;
+		/* verilator lint_off BLKSEQ */
+		FIFO_start = `L1_CACHE_SIZE'b0;
+		FIFO_end = `L1_CACHE_SIZE'b0;
+		/* verilator lint_on BLKSEQ */
+	end else if ( jump_req_latch ) begin
 		INSTRUCTION_ADDRESS <= { 4'b0 , ADDRESS_INPUT };
 		INSTRUCTION_LOCATION <= ADDRESS_INPUT;
 		func <= 1;
@@ -401,7 +397,6 @@ always @( posedge jump_req ) begin
 	FIFO_start = FIFO_end ;
 	/* verilator lint_on BLKSEQ */
 	jump_req_latch <= 1;
-	VALID_INSTRUCTION <= 0;
 end
 
 endmodule
diff --git a/system/decoder.v b/system/decoder.v
index 6a7fce6..033658e 100644
--- a/system/decoder.v
+++ b/system/decoder.v
@@ -270,8 +270,8 @@ wire [`UCODE_DATA_BITS-1:0] ucode_data;
 
 microcode ucode(seq_addr_input,ucode_data);
 
-`define invalid_instruction next_state=`EXEC_WAIT;ERROR<=`ERR_UNIMPL_INSTRUCTION;IN_MOD=3'b011;seq_addr_entry<=`UCODE_NO_INSTRUCTION;
-`define unimpl_addressing_mode next_state=`EXEC_WAIT;ERROR <= `ERR_UNIMPL_ADDRESSING_MODE;IN_MOD=3'b011;seq_addr_entry<=`UCODE_NO_INSTRUCTION;
+`define invalid_instruction next_state=`EXEC_WAIT;ERROR<=`ERR_UNIMPL_INSTRUCTION;HALT<=0;IN_MOD=3'b011;seq_addr_entry<=`UCODE_NO_INSTRUCTION;opcode_size=0;DEPENDS_ON_PREVIOUS<=0;
+`define unimpl_addressing_mode next_state=`EXEC_WAIT;ERROR <= `ERR_UNIMPL_ADDRESSING_MODE;HALT<=0;IN_MOD=3'b011;seq_addr_entry<=`UCODE_NO_INSTRUCTION;
 
 
 //TODO: A possible optimisation for instruction with 8bit parameter and
@@ -833,13 +833,14 @@ always @( FLAGS or INSTRUCTION or SIMPLE_MICRO or seq_addr_input ) begin
 				in_alu_sel2=2'b11;
 				reg_read_port1_addr={Wbit,3'b000};
 				PARAM_ACTION=`LOAD_8;
-				MEM_OR_IO=1;
 				HALT <= 0;
 				PARAM1=0;
 				OUT_MOD={3'b000};
 				DEPENDS_ON_PREVIOUS<=0;
 				IN_MOD=3'b011;
 				next_state=`EXEC_WRITE_ENTRY;
+				`normal_instruction
+				MEM_OR_IO=1;
 			end
 			11'b1100_1111_???:begin
 				/*  IRET - Return from interrupt  */
@@ -987,6 +988,7 @@ always @( FLAGS or INSTRUCTION or SIMPLE_MICRO or seq_addr_input ) begin
 		memio_address_select=ucode_data[39:39];
 		MEM_OR_IO=0;
 		HALT <= 0;
+		ERROR <= 0; //TODO probably, right?
 	end
 
 	if(PARAM_ACTION==`LOAD_8)begin