diff --git a/system/decoder.v b/system/decoder.v index 2949cae..2df346d 100644 --- a/system/decoder.v +++ b/system/decoder.v @@ -43,7 +43,7 @@ assign DATA=ucode[ADDR]; endmodule module decoder( - input wire [15:0] CIR,input wire [15:0] FLAGS, output wire [3:0] INSTRUCTION_INFO, output wire [1:0]DECODER_SIGNALS,output reg [`PROC_STATE_BITS-1:0]next_state + input wire [15:0] CIR,input wire [15:0] FLAGS, output wire [2:0] INSTRUCTION_INFO, output wire [1:0]DECODER_SIGNALS,output reg [`PROC_STATE_BITS-1:0]next_state ,output reg [2:0]IN_MOD, output reg [2:0]RM, output reg [15:0] PARAM1,output reg [15:0] PARAM2 ,output reg [1:0]in_alu1_sel1,output reg [1:0]in_alu1_sel2,output reg [2:0]OUT_MOD ,output wire [11:0]REGISTER_FILE_CONTROL @@ -58,8 +58,8 @@ reg [3:0]reg_write_addr; assign REGISTER_FILE_CONTROL={reg_write_addr,reg_read_port1_addr,reg_read_port2_addr}; /* For correct fetching of instructions and global options for the alu */ -reg Wbit,Sbit,unaligning,opcode_size; -assign INSTRUCTION_INFO={Wbit,Sbit,unaligning,opcode_size}; +reg Wbit,Sbit,opcode_size; +assign INSTRUCTION_INFO={Wbit,Sbit,opcode_size}; reg ERROR, HALT; assign DECODER_SIGNALS={ERROR,HALT}; @@ -73,8 +73,6 @@ microcode ucode(seq_addr_input,ucode_data); /* 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 */ `define invalid_instruction next_state=`PROC_IF_STATE_ENTRY;ERROR=1;IN_MOD=2'b11; -`define start_aligning_instruction unaligning=0; -`define start_unaligning_instruction unaligning=1; //TODO: A possible optimisation for instruction with 8bit parameter and //opcode_size=0 would be to set PARAM1 here instead of sending execution over @@ -90,10 +88,8 @@ always @( CIR or SIMPLE_MICRO or seq_addr_input ) begin opcode_size=0; Wbit=CIR[8:8]; if(Wbit)begin - `start_unaligning_instruction instruction_size=3; end else begin - `start_aligning_instruction instruction_size=2; end IN_MOD=2'b11; @@ -130,12 +126,10 @@ always @( CIR or SIMPLE_MICRO or seq_addr_input ) begin OUT_MOD={1'b0,IN_MOD}; case({Sbit,Wbit}) 2'b00,2'b11:begin - `start_unaligning_instruction next_state=`PROC_DE_LOAD_8_PARAM; instruction_size=3; end 2'b01:begin - `start_aligning_instruction next_state=`PROC_DE_LOAD_16_PARAM; instruction_size=4; end @@ -163,11 +157,9 @@ always @( CIR or SIMPLE_MICRO or seq_addr_input ) begin case({Sbit,Wbit}) 2'b00,2'b11:begin instruction_size=3; - `start_unaligning_instruction end 2'b01:begin instruction_size=4; - `start_aligning_instruction end 2'b10:begin `invalid_instruction @@ -191,7 +183,6 @@ always @( CIR or SIMPLE_MICRO or seq_addr_input ) begin 11'b1011_0xxx_xxx : begin /* MOV - Move Immediate byte to register */ /* 1 0 1 1 W REG | DATA | DATA if W |*/ - `start_aligning_instruction Wbit=CIR[11:11]; /* IS 0 */ instruction_size=2; opcode_size=0; @@ -207,7 +198,6 @@ always @( CIR or SIMPLE_MICRO or seq_addr_input ) begin end 11'b1011_1xxx_xxx : begin /*MOV - Move Immediate word to register*/ - `start_unaligning_instruction Wbit=CIR[11:11]; /*IS 1 */ instruction_size=3; opcode_size=0; @@ -224,7 +214,6 @@ always @( CIR or SIMPLE_MICRO or seq_addr_input ) begin 11'b1000_10xx_xxx : begin /* MOV - Reg/Mem to/from register */ /* 1 0 0 0 1 0 D W | MOD REG RM | < DISP LO > | < DISP HI > |*/ - `start_aligning_instruction opcode_size=1; instruction_size=2; RM=CIR[2:0]; @@ -272,7 +261,6 @@ always @( CIR or SIMPLE_MICRO or seq_addr_input ) begin /* | 0 1 0 0 0 REG | */ instruction_size=1; opcode_size=0; - `start_unaligning_instruction Wbit=1; in_alu1_sel1=2'b01; in_alu1_sel2=2'b00; @@ -294,7 +282,6 @@ always @( CIR or SIMPLE_MICRO or seq_addr_input ) begin /* 1 1 1 1 1 1 1 W | MOD 0 0 1 R/M | < DISP LO> | < DISP HI> */ instruction_size=2; opcode_size=1; - `start_aligning_instruction Wbit=CIR[8:8]; IN_MOD=CIR[7:6]; RM=CIR[2:0]; @@ -318,7 +305,6 @@ always @( CIR or SIMPLE_MICRO or seq_addr_input ) begin /* 1 1 1 1 0 1 0 0 | */ instruction_size=1; opcode_size=0; - `start_unaligning_instruction IN_MOD=2'b11; HALT=1; next_state=`PROC_HALT_STATE; @@ -333,10 +319,8 @@ always @( CIR or SIMPLE_MICRO or seq_addr_input ) begin opcode_size=0; if(Wbit)begin instruction_size=3; - `start_unaligning_instruction end else begin instruction_size=2; - `start_aligning_instruction end IN_MOD=2'b11; in_alu1_sel1=2'b00; @@ -361,7 +345,6 @@ always @( CIR or SIMPLE_MICRO or seq_addr_input ) begin /* 0 1 1 1 1 0 0 1 | IP-INC8 |*/ /* .... */ instruction_size=2; - `start_aligning_instruction Wbit=1; opcode_size=0; in_alu1_sel1=2'b10; @@ -407,7 +390,6 @@ always @( CIR or SIMPLE_MICRO or seq_addr_input ) begin 11'b1110_1011_xxx:begin /* JMP - Unconditional jump direct within segment (short) */ /* | 1 1 1 0 1 0 1 1 | IP-INC-LO | */ - `start_aligning_instruction instruction_size=2; opcode_size=0; Wbit=1; @@ -423,7 +405,6 @@ always @( CIR or SIMPLE_MICRO or seq_addr_input ) begin /* 1 1 0 0 1 1 0 1 | DATA |*/ instruction_size=2; opcode_size=0; - `start_aligning_instruction /* Emulate MS-DOS print routines */ if(CIR[7:0]==8'h21 && register_file.registers[0][15:8]==8'h02)begin $write("%s" ,register_file.registers[2][7:0]); /*TODO:Could trigger erroneously while CIR is not final*/ @@ -436,7 +417,6 @@ always @( CIR or SIMPLE_MICRO or seq_addr_input ) begin // Microcode instruction instruction_size=3; - `start_unaligning_instruction opcode_size=0; Wbit=1; Sbit=1; @@ -448,7 +428,6 @@ always @( CIR or SIMPLE_MICRO or seq_addr_input ) begin /* | 1 1 0 0 0 0 1 1 | */ // Microcode instruction - `start_unaligning_instruction instruction_size=1; opcode_size=0; Wbit=1; @@ -459,7 +438,6 @@ always @( CIR or SIMPLE_MICRO or seq_addr_input ) begin 11'b1010_101x_xxx:begin /* STOS - Write byte/word to [DI] and increment accordingly */ /* | 1 0 1 0 1 0 1 W | */ - `start_unaligning_instruction opcode_size=0; instruction_size=1; Wbit=CIR[8:8]; @@ -471,7 +449,6 @@ always @( CIR or SIMPLE_MICRO or seq_addr_input ) begin 11'b0101_0xxx_xxx:begin /* PUSH - SP-=2; [SP]=REG */ /* | 0 1 0 1 0 REG | */ - `start_unaligning_instruction opcode_size=0; instruction_size=1; Wbit=1; @@ -488,12 +465,10 @@ always @( CIR or SIMPLE_MICRO or seq_addr_input ) begin IN_MOD={1'b0,CIR[7:6]}; RM={CIR[2:0]}; if(Wbit==1)begin - `start_aligning_instruction instruction_size=4; next_state=`PROC_DE_LOAD_16_PARAM; end else begin instruction_size=3; - `start_unaligning_instruction next_state=`PROC_DE_LOAD_8_PARAM; end in_alu1_sel1=2'b00; /* PARAM1 */ @@ -512,7 +487,6 @@ always @( CIR or SIMPLE_MICRO or seq_addr_input ) begin 11'b0101_1xxx_xxx:begin /* POP - REG=[SP]; SP+=2 */ /* | 0 1 0 1 1 REG | */ - `start_unaligning_instruction opcode_size=0; instruction_size=1; Wbit=1; @@ -524,7 +498,6 @@ always @( CIR or SIMPLE_MICRO or seq_addr_input ) begin 11'b1111_1111_100:begin /* JMP - Unconditional indirect within segment jump */ /* 1 1 1 1 1 1 1 1 | MOD 1 0 0 R/M | < DISP-LO > | < DISP-HI > */ - `start_aligning_instruction opcode_size=1; instruction_size=2; Wbit=1; @@ -551,11 +524,9 @@ always @( CIR or SIMPLE_MICRO or seq_addr_input ) begin in_alu1_sel2=2'b11; if(Wbit==1)begin instruction_size=4; - `start_aligning_instruction; next_state=`PROC_DE_LOAD_16_PARAM; end else begin instruction_size=3; - `start_unaligning_instruction; next_state=`PROC_DE_LOAD_8_PARAM; end diff --git a/system/processor.v b/system/processor.v index 501b5c4..054a4fe 100644 --- a/system/processor.v +++ b/system/processor.v @@ -40,7 +40,7 @@ assign external_data_bus=read?data_bus_output_register:16'hz; reg [`PROC_STATE_BITS-1:0] state; /*############ Decoder ########################################################## */ -wire Wbit, Sbit, unaligning_instruction,opcode_size; +wire Wbit, Sbit, opcode_size; wire [`PROC_STATE_BITS-1:0] next_state; wire [2:0]RM; wire [15:0]DE_PARAM1;// Input param1 form decoder to alu @@ -48,7 +48,7 @@ wire [15:0]DE_PARAM2; wire DE_ERROR,DE_HALT; wire [3:0]DE_reg_read_port1_addr,DE_reg_write_addr,DE_reg_read_port2_addr; wire [11:0]DE_REGISTER_CONTROL; -wire [3:0]INSTRUCTION_INFO; +wire [2:0]INSTRUCTION_INFO; wire [1:0]DECODER_SIGNALS; wire [`UCODE_ADDR_BITS-1:0] ucode_seq_addr_entry; @@ -79,9 +79,8 @@ decoder decoder( .instruction_size(DE_instruction_size) ); -assign Wbit=INSTRUCTION_INFO[3:3]; -assign Sbit=INSTRUCTION_INFO[2:2]; -assign unaligning_instruction=INSTRUCTION_INFO[1:1]; +assign Wbit=INSTRUCTION_INFO[2:2]; +assign Sbit=INSTRUCTION_INFO[1:1]; assign opcode_size=INSTRUCTION_INFO[0:0]; assign DE_reg_write_addr=DE_REGISTER_CONTROL[11:8];