diff --git a/.gitignore b/.gitignore
index 539b6b2..34f9ce3 100644
--- a/.gitignore
+++ b/.gitignore
@@ -20,3 +20,4 @@ system/simplified_ucode.txt
 system/build/
 tools/*svg
 system/external_ip/litedram_core_ecp5_phy.v
+system/external_ip/litedram_core_ecp5_phy_sim.v
diff --git a/Makefile b/Makefile
index 471bc03..ab2d7ab 100644
--- a/Makefile
+++ b/Makefile
@@ -51,3 +51,6 @@ clean:
 
 upload: boot_code/bios.stxt
 	${Q}make ${MAKEOPTS} PRINT_PATH_PREFIX=system/ -C system upload
+
+fpga_sim: boot_code/bios.stxt
+	${Q}make ${MAKEOPTS} PRINT_PATH_PREFIX=system/ -C system fpga_sim
diff --git a/system/Makefile b/system/Makefile
index 009492a..f8c5b4b 100644
--- a/system/Makefile
+++ b/system/Makefile
@@ -20,52 +20,14 @@ INCLUDES=exec_state_def.v alu_header.v config.v ucode_header.v error_header.v
 MICROCODE=ucode.txt
 SYSTEM_VVP=system.vvp
 PRINT_PATH_PREFIX=./
+BUILD_FILES_PREFIX=build/
 
 BOOT_CODE=boot_code.txt
 VERILATOR_BIN=obj_dir/Vsystem
+VERILATOR_FPGA_BIN=/Vfpga_top
 NO_ASM=0
 include ../common.mk
 
-################################################################################
-####                           SIMULATION RECIPES                           ####
-################################################################################
-
-EVENT_SIM_TESTBENCH=testbench.v
-VERILATOR_TESTBENCH=testbench.cpp
-SIMULATION_TOP_LEVEL_SOURCE=system.v
-GTKWSAVE=../gtkwave_savefile.gtkw
-
-#build options
-VERILATOR_OPTS += --cc --exe
-
-#binary options
-VERILATOR_OPTS += --trace-fst --threads 1 --autoflush
-
-#linter options
-VERILATOR_OPTS += -Wall --Wno-DECLFILENAME
-
-#optimisation options
-VERILATOR_OPTS += -x-assign fast --x-initial fast
-#For testing use:
-#VERILATOR_OPTS += -x-assign unique --x-initial unique
-
-# COMPILING
-${SYSTEM_VVP} : ${SIMULATION_TOP_LEVEL_SOURCE} ${SOURCES} ${INCLUDES} ${EVENT_SIM_TESTBENCH}
-	${QUIET_IVERILOG}
-	${Q}iverilog -g2012 -D CALCULATE_IPC -D OUTPUT_JSON_STATISTICS -o "$@" ${SIMULATION_TOP_LEVEL_SOURCE} ${SOURCES} ${EVENT_SIM_TESTBENCH}
-
-${VERILATOR_BIN}: ${VERILATOR_BIN}.mk
-	${Q}make ${MAKEOPTS} PRINT_PATH_PREFIX=${PRINT_PATH_PREFIX}obj_dir/ OPT_FAST="-O2 -march=native -mtune=native" -C obj_dir -f ../verilator_makefile Vsystem
-
-${VERILATOR_BIN}.mk: ${VERILATOR_TESTBENCH} ${SIMULATION_TOP_LEVEL_SOURCE} ${SOURCES} ${INCLUDES}
-	${QUIET_VERILATOR}
-	${Q}verilator -DCALCULATE_IPC -DOUTPUT_JSON_STATISTICS ${VERILATOR_OPTS} $^
-
-################################################################################
-####                           FPGA/ASIC RECIPES                            ####
-################################################################################
-
-BUILD_FILES_PREFIX=build/
 $(shell mkdir -p $(BUILD_FILES_PREFIX))
 FPGA_SEED ::= $(shell seq 1 200|sort -R|head -n1)
 
@@ -86,6 +48,64 @@ else
 $(error invalid ECP5 device ${ECP5_DEVICE})
 endif
 
+EVENT_SIM_TESTBENCH=testbench.v
+VERILATOR_TESTBENCH=testbench.cpp
+SIMULATION_TOP_LEVEL_SOURCE=system.v
+GTKWSAVE=../gtkwave_savefile.gtkw
+
+SIMULATED_SOURCES ::= ${SIMULATION_TOP_LEVEL_SOURCE} ${SOURCES} ${INCLUDES}
+FPGA_SIM_SOURCES ::= fpga_config/${FPGA_BOARD}/fpga_top.v ${SOURCES} ${FPGA_SOC_SIM_SOURCES} ${INCLUDES}
+FPGA_SOURCES ::= fpga_config/${FPGA_BOARD}/fpga_top.v ${SOURCES} ${FPGA_SOC_SOURCES} ${INCLUDES}
+
+#build options
+VERILATOR_OPTS += --cc --exe
+
+#binary options
+VERILATOR_OPTS += --trace-fst --threads 1 --autoflush
+
+#linter options
+VERILATOR_OPTS += -Wall --Wno-DECLFILENAME
+
+#optimisation options
+VERILATOR_OPTS += -x-assign fast --x-initial fast
+#For testing use:
+#VERILATOR_OPTS += -x-assign unique --x-initial unique
+
+
+################################################################################
+####                           SIMULATION RECIPES                           ####
+################################################################################
+
+# COMPILING
+${SYSTEM_VVP} : ${SIMULATED_SOURCES} ${EVENT_SIM_TESTBENCH}
+	${QUIET_IVERILOG}
+	${Q}iverilog -g2012 -D CALCULATE_IPC -D OUTPUT_JSON_STATISTICS -o "$@" ${SIMULATION_TOP_LEVEL_SOURCE} ${SOURCES} ${EVENT_SIM_TESTBENCH}
+
+${VERILATOR_BIN}: ${VERILATOR_BIN}.mk
+	${Q}make ${MAKEOPTS} PRINT_PATH_PREFIX=${PRINT_PATH_PREFIX}obj_dir/ OPT_FAST="-O2 -march=native -mtune=native" -C obj_dir -f ../verilator_makefile Vsystem
+
+${VERILATOR_BIN}.mk: ${VERILATOR_TESTBENCH} ${SIMULATED_SOURCES}
+	${QUIET_VERILATOR}
+	mkdir -p ${BUILD_FILES_PREFIX}/sim_${FPGA_BOARD}/
+	${Q}verilator -DCALCULATE_IPC -DOUTPUT_JSON_STATISTICS ${VERILATOR_OPTS} $^
+
+${BUILD_FILES_PREFIX}/sim_${FPGA_BOARD}/${VERILATOR_FPGA_BIN}: ${BUILD_FILES_PREFIX}/sim_${FPGA_BOARD}/${VERILATOR_FPGA_BIN}.mk
+	${Q}make ${MAKEOPTS} PRINT_PATH_PREFIX=${PRINT_PATH_PREFIX}${BUILD_FILES_PREFIX}/sim_${FPGA_BOARD}/ OPT_FAST="-O2 -march=native -mtune=native" -C "${BUILD_FILES_PREFIX}/sim_${FPGA_BOARD}/" -f ../../verilator_makefile_fpga Vfpga_top
+
+${BUILD_FILES_PREFIX}/sim_${FPGA_BOARD}/${VERILATOR_FPGA_BIN}.mk: fpga_config/${FPGA_BOARD}/testbench.cpp ${FPGA_SIM_SOURCES}
+	${QUIET_VERILATOR}
+	mkdir -p "${BUILD_FILES_PREFIX}/sim_${FPGA_BOARD}/"
+	${Q}verilator -DCALCULATE_IPC -DOUTPUT_JSON_STATISTICS --Mdir ${BUILD_FILES_PREFIX}/sim_${FPGA_BOARD}/ ${VERILATOR_OPTS} ../../fpga_config/${FPGA_BOARD}/testbench.cpp ${FPGA_SIM_SOURCES}
+
+.PHONY: fpga_sim
+fpga_sim fpga_sim.fst: ${BUILD_FILES_PREFIX}/sim_${FPGA_BOARD}/${VERILATOR_FPGA_BIN} ${MICROCODE} simplified_ucode.txt ../boot_code/bios.stxt
+	$(call QUIET_VERILATOR_RUN,$(word 2,$^),$<)
+	${Q} ${NUMACTL} "${BUILD_FILES_PREFIX}/sim_${FPGA_BOARD}/${VERILATOR_FPGA_BIN}" +VERSION=${VERSION} +WAVEFORM="fpga_sim.fst" +COMMIT=${COMMIT} +BOOT_CODE="../boot_code/bios.stxt" +MICROCODE="simplified_ucode.txt"
+
+################################################################################
+####                           FPGA/ASIC RECIPES                            ####
+################################################################################
+
 simplified_ucode.txt:ucode.txt
 	${Q}tr 'x' '0' < $^ | sed 's@//.*@@' | grep ^@ |sort | sed 's/.* .//;s/ $$//' | tr -d _ > $@
 
@@ -93,15 +113,17 @@ external_ip/litedram_core_ecp5_phy.v:
 	${QUIET_DOWNLOAD}
 	${Q}../tools/gen_litedram.sh -q "$@"
 
+external_ip/litedram_core_ecp5_phy_sim.v:
+	${QUIET_DOWNLOAD}
+	${Q}../tools/gen_litedram.sh --simulation -q "$@"
+
 #########################################
 ##     SYNTHESIS  RECIPES
 
-SYNTHESIS_SOURCES ::= ${SOURCES} fpga_config/${FPGA_BOARD}/fpga_top.v ${SOC_SYNTHESIS_SOURCES} ${INCLUDES}
-
 #TODO: we are relying on yosys to trim the input program txt file and hope its enough for the whole program...
-${BUILD_FILES_PREFIX}synth_ecp5_${FPGA_BOARD}.json: ${SYNTHESIS_SOURCES} ${FPGA_BOOTCODE} simplified_ucode.txt
+${BUILD_FILES_PREFIX}synth_ecp5_${FPGA_BOARD}.json: ${FPGA_SOURCES} ${FPGA_BOOTCODE} simplified_ucode.txt
 	${QUIET_YOSYS}
-	${Q} yosys -q -p 'read_verilog -defer -noautowire -sv '"${SYNTHESIS_SOURCES}; attrmap -tocase keep -imap keep="true" keep=1 -imap keep="false" keep=0 -remove keep=0; synth_ecp5 -json \"$@\" -abc9 -top fpga_top"
+	${Q} yosys -q -p 'read_verilog -defer -noautowire -sv '"${FPGA_SOURCES}; attrmap -tocase keep -imap keep="true" keep=1 -imap keep="false" keep=0 -remove keep=0; synth_ecp5 -json \"$@\" -abc9 -top fpga_top"
 
 ##########################################
 ##     PLACE AND ROUTE RECIPES
diff --git a/system/fpga_config/OrangeCrab_r0.2.1/config.mk b/system/fpga_config/OrangeCrab_r0.2.1/config.mk
index cd0a49d..bdee2fc 100644
--- a/system/fpga_config/OrangeCrab_r0.2.1/config.mk
+++ b/system/fpga_config/OrangeCrab_r0.2.1/config.mk
@@ -18,7 +18,11 @@ ECP5_SPEED_GRADE=8
 
 ########   End of user configuration   ########
 
-SOC_SYNTHESIS_SOURCES=peripherals/I2C_driver.v peripherals/ascii_to_HD44780_driver.v peripherals/pcf8574_for_HD44780.v peripherals/Wishbone_IO_driver.v peripherals/Wishbone_memory_driver.v external_ip/litedram_core_ecp5_phy.v
+#NOT USED OUTSIDE OF HERE
+FPGA_SOC_COMMON_SOURCES=peripherals/I2C_driver.v peripherals/ascii_to_HD44780_driver.v peripherals/pcf8574_for_HD44780.v peripherals/Wishbone_IO_driver.v peripherals/Wishbone_memory_driver.v
+
+FPGA_SOC_SOURCES=${FPGA_SOC_COMMON_SOURCES} external_ip/litedram_core_ecp5_phy.v
+FPGA_SOC_SIM_SOURCES=${FPGA_SOC_COMMON_SOURCES} fpga_config/OrangeCrab_r0.2.1/verilator_config.vlt external_ip/litedram_core_ecp5_phy_sim.v
 
 FPGA_BOOTCODE=../boot_code/bios.stxt
 
diff --git a/system/fpga_config/OrangeCrab_r0.2.1/fpga_top.v b/system/fpga_config/OrangeCrab_r0.2.1/fpga_top.v
index 1c2e1ed..201e689 100644
--- a/system/fpga_config/OrangeCrab_r0.2.1/fpga_top.v
+++ b/system/fpga_config/OrangeCrab_r0.2.1/fpga_top.v
@@ -31,6 +31,7 @@ module fpga_top(
 	output rgb_led0_g,
 	output rgb_led0_b,
 
+`ifdef SYNTHESIS
 	output wire   [15:0] ddram_a, // [15:13] are unused in litex as well, they just also route them through a trellis block
 	output wire    [2:0] ddram_ba,
 	output wire          ddram_cas_n,
@@ -49,11 +50,53 @@ module fpga_top(
 
 	inout gpio_0,/*sda*/
 	output gpio_1 /*scl*/
+`else
+	output i2c_dir,
+	output i2c_scl,
+	input i2c_sda_in,
+	output i2c_sda_out
+`endif
 );
 
+`ifndef SYNTHESIS
+string waveform_name;
+initial begin
+	if($value$plusargs("WAVEFORM=%s",waveform_name))begin
+		$dumpfile(waveform_name);
+		$dumpvars(0,p,cycles);
+	end
+end
+//TODO: should there be some common file between all the fpga_tops and system.v for this stuff?
+always @(posedge clk48) begin
+	if(HALT==1&&disp_cache_start==disp_cache_end)begin
+		$finish;
+	end
+end
+reg sane;
+always @(posedge reset)begin sane<=1; end
+always @( ERROR ) begin
+	if ( ERROR != `ERR_NO_ERROR && sane == 1 ) begin
+			$display("PROCESSOR RUN INTO AN ERROR.");
+			case (ERROR)
+				default:begin
+				end
+				`ERR_UNIMPL_INSTRUCTION:begin
+					$display("Unimplemented instruction");
+				end
+				`ERR_UNIMPL_ADDRESSING_MODE: begin
+					$display("Unimplemented addressing mode");
+				end
+			endcase
+			$finish;
+	end
+end
+`endif
+
+`ifdef SYNTHESIS
 assign ddram_a[15:13] = 3'b0;
 assign ddram_vccio = 6'd63;
 assign ddram_gnd = 2'd0;
+`endif
 
 wire HALT;
 wire [`ERROR_BITS-1:0]ERROR;
@@ -85,6 +128,7 @@ processor p(
 `endif
 );
 
+/* verilator lint_off UNUSEDSIGNAL */
 `ifdef CALCULATE_IPC
 wire new_instruction;
 `endif
@@ -93,6 +137,9 @@ wire [`L1_CACHE_SIZE-1:0]L1_SIZE_STAT;
 wire VALID_INSTRUCTION_STAT;
 wire jump_req_debug;
 `endif
+/* verilator lint_on UNUSEDSIGNAL */
+
+
 reg [2:0]rgb_led_color;
 assign rgb_led0_r=rgb_led_color[0];
 assign rgb_led0_g=rgb_led_color[1];
@@ -158,12 +205,15 @@ always @(posedge CPU_SPEED)begin
 			disp_cache_end<=disp_cache_end+7'd1;
 		end else if(IOMEM==1'b1 && address_bus[7:0]==8'hB0 )begin
 			if(data_bus_write[0:0]==1)
-				rgb_led_color=3'b000;
+				rgb_led_color<=3'b000;
 			else
-				rgb_led_color=3'b111;
+				rgb_led_color<=3'b111;
 		end
 	end else if(ascii_state==1'b0)begin
 		if(ascii_data_ready&disp_cache_start!=disp_cache_end)begin
+`ifndef SYNTHESIS
+			$write("%s" ,disp_write_cache[disp_cache_start]); // TODO: maybe simulate the i2c lcd
+`endif
 			ascii_data<=disp_write_cache[disp_cache_start];
 			disp_cache_start<=disp_cache_start+7'd1;
 			ascii_data_write_req<=1;
@@ -218,13 +268,14 @@ assign wishbone_cs=!((IOMEM==1)&&(address_bus[7:4] == 4'h4));
 /// DDR3 Controller
 
 wire ddr3_init_done,ddr3_init_error,ddr3_pll_locked;
-
-wire [31:0] ddr3_read_data;
-wire [31:0] ddr3_write_data;
-
-reg [15:0]DDR3_data_bus_read;
-
-assign ddr3_write_data={16'd0,data_bus_write};
+/* verilator lint_off UNUSEDSIGNAL */
+wire user_rst;
+/* verilator lint_on UNUSEDSIGNAL */
+`ifndef SYNTHESIS
+assign ddr3_pll_locked=1;
+wire sim_trace;
+assign sim_trace=0;//signal is not connected on litedram, not sure what was the idea behind it
+`endif
 
 wire [15:0]Wishbone_driver_data_bus_read;
 wire [15:0]Wishbone_driver_data_bus_write=data_bus_write;
@@ -317,9 +368,15 @@ litedram_core DDR3_RAM_DRIVER(
 	//////  GENERAL ///////
 	.clk(clk48),
 	.user_clk(CPU_SPEED),
+`ifdef SYNTHESIS
 	.rst(!reset),
+	.pll_locked(ddr3_pll_locked),
+`else
+	.sim_trace(sim_trace),
+`endif
 
 	//////  DDR3 INTERFACE //////
+`ifdef SYNTHESIS
 	.ddram_a(ddram_a[12:0]), //also ignored on the litedram core
 	.ddram_ba(ddram_ba),
 	.ddram_cas_n(ddram_cas_n),
@@ -335,6 +392,7 @@ litedram_core DDR3_RAM_DRIVER(
 	.ddram_ras_n(ddram_ras_n),
 	.ddram_reset_n(ddram_reset_n),
 	.ddram_we_n(ddram_we_n),
+`endif
 
 	/////// SYSTEM MEMORY INTERFACE ////////////////
 	.init_done(ddr3_init_done),
@@ -348,8 +406,7 @@ litedram_core DDR3_RAM_DRIVER(
 	.user_port_wishbone_0_sel(wb_mem_sel),
 	.user_port_wishbone_0_stb(wb_mem_stb),
 	.user_port_wishbone_0_we(wb_mem_we),
-	.pll_locked(ddr3_pll_locked),
-	//output wire          user_rst,
+	.user_rst(user_rst),
 
 	/////// WISHBONE CONTROL INTERFACE ///////////
 	.wb_ctrl_ack(wb_ctrl_ack),
@@ -412,8 +469,8 @@ pcf8574_for_HD44780 PCF8574_driver(
 
 // I2C driver
 
-wire SCL,SDA_input,SDA_output,SDA_direction,I2C_BUSY,I2C_SEND;
-assign gpio_1=SCL;
+wire SDA_direction;
+wire SCL,SDA_input,SDA_output,I2C_BUSY,I2C_SEND;
 
 I2C_driver i2c_driver(
 	.clock(I2C_SPEED),
@@ -429,6 +486,8 @@ I2C_driver i2c_driver(
 	.i2c_data(i2c_data)
 );
 
+`ifdef SYNTHESIS
+
 TRELLIS_IO #(
 	// Parameters.
 	.DIR ("BIDIR")
@@ -443,5 +502,16 @@ TRELLIS_IO #(
 	.O (SDA_input)
 );
 
+assign gpio_1=SCL;
+
+`else
+
+assign i2c_dir=SDA_direction;
+assign i2c_scl=SCL;
+assign SDA_input=i2c_sda_in;
+assign i2c_sda_out=SDA_output;
+
+`endif
+
 
 endmodule
diff --git a/system/fpga_config/OrangeCrab_r0.2.1/testbench.cpp b/system/fpga_config/OrangeCrab_r0.2.1/testbench.cpp
new file mode 100644
index 0000000..99aaf3b
--- /dev/null
+++ b/system/fpga_config/OrangeCrab_r0.2.1/testbench.cpp
@@ -0,0 +1,54 @@
+#include "Vfpga_top.h"
+#include "verilated.h"
+#include "stdio.h"
+
+Vfpga_top *system_state;
+VerilatedContext* contextp;
+
+/*In hz */
+#define CPU_SPEED 1000
+
+#define timeinc CPU_SPEED*1000000/2
+
+void tick() {
+	system_state->clk48 = 1;
+	contextp->timeInc(timeinc);
+	system_state->eval();
+	system_state->clk48 = 0;
+	contextp->timeInc(timeinc);
+	system_state->eval();
+}
+
+int main(int argc, char** argv) {
+	contextp = new VerilatedContext;
+
+	// Set debug level, 0 is off, 9 is highest presently used
+	// May be overridden by commandArgs argument parsing
+	contextp->debug(0);
+
+	// Verilator must compute traced signals
+	contextp->traceEverOn(true);
+
+	contextp->commandArgs(argc, argv);
+	system_state = new Vfpga_top{contextp};
+	system_state->user_button=1;
+
+	//system_state->reset=1;
+	tick();
+	//system_state->reset=0;
+	tick();
+	tick();
+	//system_state->reset=1;
+
+	// Simulate until $finish
+	while(!contextp->gotFinish()){
+		tick();
+	}
+
+	system_state->final();
+
+	delete system_state;
+	delete contextp;
+	return 0;
+}
+
diff --git a/system/fpga_config/OrangeCrab_r0.2.1/verilator_config.vlt b/system/fpga_config/OrangeCrab_r0.2.1/verilator_config.vlt
new file mode 100644
index 0000000..8ca3a1a
--- /dev/null
+++ b/system/fpga_config/OrangeCrab_r0.2.1/verilator_config.vlt
@@ -0,0 +1,6 @@
+`verilator_config
+lint_off -rule COMBDLY -file "external_ip/litedram_core_ecp5_phy_sim.v"
+lint_off -rule CASEINCOMPLETE -file "external_ip/litedram_core_ecp5_phy_sim.v"
+lint_off -rule UNUSEDSIGNAL -file "external_ip/litedram_core_ecp5_phy_sim.v"
+lint_off -rule WIDTHEXPAND -file "external_ip/litedram_core_ecp5_phy_sim.v"
+lint_off -rule WIDTHTRUNC -file "external_ip/litedram_core_ecp5_phy_sim.v"
diff --git a/system/memory.v b/system/memory.v
index cc79d1b..d233c75 100644
--- a/system/memory.v
+++ b/system/memory.v
@@ -45,7 +45,7 @@ initial begin
 		$display("No boot code specified. Please add +BOOT_CODE=<path> to your vvp args");
 		$finish;
 	end
-	$readmemh(boot_code, memory,0,32767);
+	$readmemh(boot_code, memory,0,(RAM_SIZE_IN_BYTES/2)-1);
 `else
 	//TODO: don't have it hard coded
 	$readmemh("../boot_code/bios.stxt", memory,0,(RAM_SIZE_IN_BYTES/2)-1); // 2KiB
diff --git a/system/peripherals/I2C_driver.v b/system/peripherals/I2C_driver.v
index 96a012c..b9e4554 100644
--- a/system/peripherals/I2C_driver.v
+++ b/system/peripherals/I2C_driver.v
@@ -19,7 +19,9 @@
 
 module I2C_driver (
 	input wire clock,
+/* verilator lint_off UNUSEDSIGNAL */
 	input wire SDA_input,
+/* verilator lint_on UNUSEDSIGNAL */
 	output wire SDA_output,
 	output reg SDA_direction, //1:output 0:input
 	output reg SCL,
diff --git a/system/peripherals/Wishbone_memory_driver.v b/system/peripherals/Wishbone_memory_driver.v
index d1ebe20..19fa49d 100644
--- a/system/peripherals/Wishbone_memory_driver.v
+++ b/system/peripherals/Wishbone_memory_driver.v
@@ -19,7 +19,10 @@
 
 module Wishbone_memory_driver (
 	input wire clock,
+
+/* verilator lint_off UNUSEDSIGNAL */
 	input wire reset_n,
+/* verilator lint_on UNUSEDSIGNAL */
 
 	input wire [19:0] address,
 	input wire [15:0] data_bus_in,
@@ -33,12 +36,18 @@ module Wishbone_memory_driver (
 	input  wire          wb_mem_ack,
 	output wire   [24:0] wb_mem_adr,
 	output reg          wb_mem_cyc,
+
 /* verilator lint_off UNUSEDSIGNAL */
 // I don't yet use the upper word
 	input  wire   [31:0] wb_mem_data_r,
 /* verilator lint_on UNUSEDSIGNAL */
+
 	output wire   [31:0] wb_mem_data_w,
+
+/* verilator lint_off UNUSEDSIGNAL */
 	input  wire          wb_mem_err,
+/* verilator lint_on UNUSEDSIGNAL */
+
 	output wire    [3:0] wb_mem_sel,
 	output reg          wb_mem_stb,
 	output wire          wb_mem_we
@@ -53,7 +62,7 @@ always @(posedge clock)begin
 end
 
 always @(posedge wb_mem_ack)begin
-		data_bus_out=wb_mem_data_r[15:0];
+	data_bus_out<=wb_mem_data_r[15:0];
 end
 assign wb_mem_data_w={16'd0,data_bus_in};
 
diff --git a/system/peripherals/pcf8574_for_HD44780.v b/system/peripherals/pcf8574_for_HD44780.v
index cb93706..20913e5 100644
--- a/system/peripherals/pcf8574_for_HD44780.v
+++ b/system/peripherals/pcf8574_for_HD44780.v
@@ -26,7 +26,9 @@ input wire pcf_write_req,
 input wire pcf_command_data,
 input wire [3:0]pcf_data,
 output reg pcf_busy=0,
+/* verilator lint_off UNUSEDSIGNAL */
 input new_backlight,
+/* verilator lint_on UNUSEDSIGNAL */
 input  backlight_update,
 
 input I2C_BUSY,
diff --git a/system/verilator_makefile_fpga b/system/verilator_makefile_fpga
new file mode 100644
index 0000000..ce55106
--- /dev/null
+++ b/system/verilator_makefile_fpga
@@ -0,0 +1,21 @@
+# This file is basically to make verilator compilation look pretty.
+# If the project doesn't compile it might be because verilator handles compilation
+# differently and this patch doesn't work anymore. In such case remove everything
+# except the include Vsystem.mk line and try again.
+VM_DEFAULT_RULES=0
+
+include Vfpga_top.mk
+
+include ../../../common.mk
+
+%.o: %.cpp
+	${QUIET_CC}
+	${Q}$(OBJCACHE) $(CXX) $(CXXFLAGS) $(CPPFLAGS) $(OPT_FAST) -c -o $@ $<
+
+$(VK_SLOW_OBJS): %.o: %.cpp
+	${QUIET_CC}
+	${Q}$(OBJCACHE) $(CXX) $(CXXFLAGS) $(CPPFLAGS) $(OPT_SLOW) -c -o $@ $<
+
+$(VK_GLOBAL_OBJS): %.o: %.cpp
+	${QUIET_CC}
+	${Q}$(OBJCACHE) $(CXX) $(CXXFLAGS) $(CPPFLAGS) $(OPT_GLOBAL) -c -o $@ $<
diff --git a/tools/gen_litedram.sh b/tools/gen_litedram.sh
index 50b7c79..a377747 100755
--- a/tools/gen_litedram.sh
+++ b/tools/gen_litedram.sh
@@ -7,6 +7,7 @@ PYTHON_APPIMAGE_URL=https://github.com/niess/python-appimage/releases/download/p
 PYTHON_APPIMAGE_SUM=8c383ade3ace416cf508d5f458b30149
 
 OUTPUT_ECP5_1_WISHBONE_MD5=c775ddb23fd97211f3ace40d6e8c2a5f
+OUTPUT_ECP5_1_WISHBONE_SIM_MD5=06d0b073d06937312b425767c1895c6c
 
 
 help(){
@@ -21,6 +22,7 @@ STOP_PARSING=0
 OUT_FILE=""
 QUIET=0
 FORCE=0
+SIMULATION=0
 while [ $# -gt 0 ]; do
 	if [ "$STOP_PARSING" = "1" ]
 	then
@@ -41,6 +43,10 @@ while [ $# -gt 0 ]; do
 			FORCE=1
 			shift
 			;;
+		-s|--simulation)
+			SIMULATION=1
+			shift
+			;;
 		--)
 			if ! [ $# -gt 1 ]
 			then
@@ -125,6 +131,17 @@ PYTHON=$(realpath squashfs-root/AppRun)
 mkdir python_modules
 PYTHON_MODULES=$(realpath python_modules)
 
+######### This is a patch ############
+# It's because litedram needs modules
+# it doesn't really use for --sim and
+# pip doesn't currently have some
+wget --quiet https://github.com/enjoy-digital/litescope/archive/refs/tags/2023.08.tar.gz
+tar xf 2023.08.tar.gz
+mv litescope-2023.08/litescope/ "${PYTHON_MODULES}"
+rm -r litescope-2023.08 2023.08.tar.gz
+######################################
+
+
 if [ "$QUIET" = 0 ];then
 	echo extracting the source...
 fi
@@ -148,7 +165,7 @@ if [ "$QUIET" = 0 ];then
 	echo Downloading required python modules...
 fi
 
-if ! "$PYTHON" -m pip install --target "$PYTHON_MODULES" install "pyaml==23.9.7" "migen==0.9.2" "litex==2023.08" "litedram==2023.8" > "$TEMP_DIR/build_log" 2> "$TEMP_DIR/build_log"
+if ! "$PYTHON" -m pip install --target "$PYTHON_MODULES" install "pyaml==23.9.7" "migen==0.9.2" "litex==2023.08" "litedram==2023.8" "liteeth==2022.12" "liteiclink==2022.12" "pythondata_misc_tapcfg" > "$TEMP_DIR/build_log" 2> "$TEMP_DIR/build_log"
 then
 	echo ERROR: Failed download python modules
 	cat "$TEMP_DIR/build_log"
@@ -164,7 +181,14 @@ fi
 
 cd build/lib/litedram/
 
-if ! PYTHONPATH=$PYTHON_MODULES "$PYTHON"  gen.py ../../../examples/orangecrab_9086.yml --no-compile-software  > "$TEMP_DIR/build_log" 2> "$TEMP_DIR/build_log"
+GEN_OPTIONS=""
+
+if [ $SIMULATION = 1 ]
+then
+	GEN_OPTIONS="$GEN_OPTIONS --sim"
+fi
+
+if ! PYTHONPATH=$PYTHON_MODULES "$PYTHON"  gen.py $GEN_OPTIONS ../../../examples/orangecrab_9086.yml --no-compile-software  > "$TEMP_DIR/build_log" 2> "$TEMP_DIR/build_log"
 then
 	echo ERROR: Failed to run gen.py
 	cat "$TEMP_DIR/build_log"
@@ -174,10 +198,18 @@ fi
 if [ "$QUIET" = 0 ];then
 	echo patching source file...
 fi
-#This is just for some yosys warnings...
-echo H4sIAAAAAAACA82T326CMBTG73mKc7XBECnKAHUkvMeyNEdatZE/hiLEzPnsa5nL4pYh3izrTduc3/d9Jyet4ziw3IuMuWuseYsVdzNRc1ZhTtOy4uMGJmQydTzPmYRAgrkfzEk4noYzEgZh5INN1DJs2waX8cYt9lkG3yWRUo1nj5FPvMALzpIkASci/nQUgt3tASSJASilWBfw+tmFboKylaA7j7YVwxpH8LNGzrU3iC+roqh5tcKU01bXF/8igOYot30pHaCjzFNfGG25tTCcvw4EzFo8SEjMBwuWfC0KA/S6UKabspRqyxltMBNMwlMM0T0jiyHwM3nRvHlBLbHY5phuRMHJFwt3YJpXwB0eshIZFVJfleK39BaLWh+k1dmehhpXKLXgNIxOUVrWDbyauuKP/V1jWotG/WFlbRzhholUHBnEcb+7hj6GMti3rRR51bijVM+Weljv0yEXHY0EAAA= | base64 -d | gzip -d | patch -s -p0
 
-if ! [ "$(sed 's@//.*@@' build/gateware/litedram_core.v | md5sum )" = "$OUTPUT_ECP5_1_WISHBONE_MD5  -" ]
+if [ "$SIMULATION" = 0 ]
+then
+	#This is just for some yosys warnings...
+	echo H4sIAAAAAAACA82T326CMBTG73mKc7XBECnKAHUkvMeyNEdatZE/hiLEzPnsa5nL4pYh3izrTduc3/d9Jyet4ziw3IuMuWuseYsVdzNRc1ZhTtOy4uMGJmQydTzPmYRAgrkfzEk4noYzEgZh5INN1DJs2waX8cYt9lkG3yWRUo1nj5FPvMALzpIkASci/nQUgt3tASSJASilWBfw+tmFboKylaA7j7YVwxpH8LNGzrU3iC+roqh5tcKU01bXF/8igOYot30pHaCjzFNfGG25tTCcvw4EzFo8SEjMBwuWfC0KA/S6UKabspRqyxltMBNMwlMM0T0jiyHwM3nRvHlBLbHY5phuRMHJFwt3YJpXwB0eshIZFVJfleK39BaLWh+k1dmehhpXKLXgNIxOUVrWDbyauuKP/V1jWotG/WFlbRzhholUHBnEcb+7hj6GMti3rRR51bijVM+Weljv0yEXHY0EAAA= | base64 -d | gzip -d | patch -s -p0
+	CHECK_MD5SUM=$OUTPUT_ECP5_1_WISHBONE_MD5
+else
+	echo H4sIAAAAAAACA7WPOQ7CMBREe59ievPjPVvlC3AGMLGFIpkEZeP6pKBCoguvmPLNDBHhtvY5intY0itMSeR+SXEKj0s3TqnYAGipDSlNsoIqW2laVxWNaXTZWKfB5Q7jnEPEtIlhzRk/+BLZ1srCVLYuldPVR+Q9SJlTDb6ng/cMQtChMEbXpX+kuQs5QQ0zBNRzZsTo8Kp9PM5jXHP6x483iNz1Tr8BAAA= | base64 -d | gzip -d | patch -s -p0
+	CHECK_MD5SUM=$OUTPUT_ECP5_1_WISHBONE_SIM_MD5
+fi
+
+if ! [ "$(sed 's@//.*@@' build/gateware/litedram_core.v | md5sum )" = "$CHECK_MD5SUM  -" ]
 then
 	if [ "$FORCE" = 0 ]
 	then