From 43f3e16ca486434f46aebd3e87d70157ddd9b25f Mon Sep 17 00:00:00 2001 From: "(Tim) Efthimis Kritikos" Date: Thu, 2 Nov 2023 21:48:12 +0000 Subject: [PATCH] Removed all instances of inout since from what i understand it's mostly synthesisable --- system/biu.v | 55 +++++++++++++++++++++------------------------- system/execute.v | 10 ++++----- system/memory.v | 10 ++++----- system/processor.v | 21 +++++++++--------- system/system.v | 13 +++++++---- system/testbench.v | 5 +++-- 6 files changed, 57 insertions(+), 57 deletions(-) diff --git a/system/biu.v b/system/biu.v index 4e1779a..5b4fafb 100644 --- a/system/biu.v +++ b/system/biu.v @@ -45,21 +45,21 @@ module BIU ( /**************** OUTSIDE WORLD ****************/ /* */ ,output wire [19:0] external_address_bus - /* */ ,inout [15:0] external_data_bus,output reg read, output reg write,output reg BHE,output reg IOMEM + /* */ ,input [15:0] external_data_bus_read,output [15:0] external_data_bus_write,output reg read, output reg write,output reg BHE,output reg IOMEM /**************** OUTPUT TO DE ****************/ /* */ ,output reg [31:0] INSTRUCTION, output reg VALID_INSTRUCTION, output reg [15:0] INSTRUCTION_LOCATION - /* */ ,output reg VALID_DATA, output reg DATA_DIR + /* */ ,output reg VALID_DATA /**************** INPUT FROM DE ****************/ ,input Wbit, input MEM_OR_IO, input valid_instruction_ack /**************** INPUT FROM EX ****************/ /* */ ,input jump_req, input write_request, input read_request - /* */ ,input[15:0] ADDRESS_INPUT + /* */ ,input[15:0] ADDRESS_INPUT, input [15:0] DATA_EX_WRITE - /************ BIDIRECTIONAL WITH EX ************/ - /* */ ,inout [15:0] DATA + /**************** OTUPUT TO EX *****************/ + /* */ ,output [15:0] DATA_EX_READ `ifdef OTUPUT_JSON_STATISTICS /***************** STATISTICS *****************/ @@ -74,10 +74,10 @@ assign VALID_INSTRUCTION_STAT = ((Isit1==1) && (FIFO_SIZE!=0) && `EARLY_VALID_IN `endif reg [15:0] data_bus_output_register; -assign external_data_bus=read?data_bus_output_register:16'hz; +assign external_data_bus_write=data_bus_output_register; //TODO: should we rename reg [15:0] DATA_OUT; -assign DATA=DATA_DIR ? 16'hz:DATA_OUT; +assign DATA_EX_READ=DATA_OUT; //TODO should we ranme `define FIFO_SIZE_BYTES $rtoi($pow(2,`L1_CACHE_SIZE)) @@ -126,7 +126,6 @@ always @(posedge clock) begin if (write_request) begin func<=0; DATA_ADDRESS <= { 4'b0 , ADDRESS_INPUT }; - DATA_DIR <= 1 ; IOMEM <= MEM_OR_IO; biu_state <= (Wbit==0) ? `BIU_PUT_BYTE : (ADDRESS_INPUT[0:0]?`BIU_PUT_UNALIGNED_16BIT_DATA:`BIU_PUT_ALIGNED_16BIT_DATA) ; INSTRUCTION_ADDRESS <= {4'b0,INSTRUCTION_LOCATION} ; @@ -136,7 +135,6 @@ always @(posedge clock) begin end else if ( read_request ) begin func<=0; DATA_ADDRESS <= { 4'b0 , ADDRESS_INPUT }; - DATA_DIR <= 0; IOMEM <= MEM_OR_IO; read <= 0; BHE <= 0; @@ -162,20 +160,20 @@ always @(posedge clock) begin `BIU_READ: begin if(INSTRUCTION_ADDRESS[0:0]==0 && FIFO_SIZE<{{(`L1_CACHE_SIZE-1){1'b1}},1'b0})begin /* verilator lint_off BLKSEQ */ - INPUT_FIFO[FIFO_end] = external_data_bus[7:0]; - INPUT_FIFO[FIFO_end+`L1_CACHE_SIZE'd1] = external_data_bus[15:8]; + INPUT_FIFO[FIFO_end] = external_data_bus_read[7:0]; + INPUT_FIFO[FIFO_end+`L1_CACHE_SIZE'd1] = external_data_bus_read[15:8]; FIFO_end = FIFO_end+`L1_CACHE_SIZE'd2; /* verilator lint_on BLKSEQ */ INSTRUCTION_ADDRESS <= INSTRUCTION_ADDRESS+20'd2; end else if(INSTRUCTION_ADDRESS[0:0]==0)begin /* verilator lint_off BLKSEQ */ - INPUT_FIFO[FIFO_end] = external_data_bus[7:0]; + INPUT_FIFO[FIFO_end] = external_data_bus_read[7:0]; FIFO_end = FIFO_end+`L1_CACHE_SIZE'd1; /* verilator lint_on BLKSEQ */ INSTRUCTION_ADDRESS <= INSTRUCTION_ADDRESS+20'd1; end else begin /* verilator lint_off BLKSEQ */ - INPUT_FIFO[FIFO_end] = external_data_bus[15:8]; + INPUT_FIFO[FIFO_end] = external_data_bus_read[15:8]; FIFO_end = FIFO_end+`L1_CACHE_SIZE'd1; /* verilator lint_on BLKSEQ */ INSTRUCTION_ADDRESS <= INSTRUCTION_ADDRESS+20'd1; @@ -188,10 +186,10 @@ always @(posedge clock) begin //TODO TODO TODO flush fifo, self modifying code `BIU_PUT_UNALIGNED_16BIT_DATA:begin `ifdef DEBUG_DATA_READ_WRITES - $display("Writing 16bit %04x at %04x",DATA,DATA_ADDRESS); + $display("Writing 16bit %04x at %04x",DATA_EX_WRITE,DATA_ADDRESS); `endif BHE <= 0; - data_bus_output_register <= {DATA[7:0],DATA[15:8]}; + data_bus_output_register <= {DATA_EX_WRITE[7:0],DATA_EX_WRITE[15:8]}; write <= 0; biu_state <= `BIU_PUT_UNALIGNED_PREP_NEXT2; end @@ -203,22 +201,22 @@ always @(posedge clock) begin end `BIU_PUT_ALIGNED_16BIT_DATA:begin `ifdef DEBUG_DATA_READ_WRITES - $display("Writing 16bit %04x at %04x",DATA,DATA_ADDRESS); + $display("Writing 16bit %04x at %04x",DATA_EX_WRTIE,DATA_ADDRESS); `endif - data_bus_output_register <= {DATA[15:8],DATA[7:0]}; + data_bus_output_register <= {DATA_EX_WRITE[15:8],DATA_EX_WRITE[7:0]}; write <= 0; biu_state <= `BIU_WRITE_RELEASE; end `BIU_PUT_BYTE:begin `ifdef DEBUG_DATA_READ_WRITES - $display("Writing 8bit %02x at %04x",DATA[7:0],DATA_ADDRESS); + $display("Writing 8bit %02x at %04x",DATA_EX_WRITE[7:0],DATA_ADDRESS); `endif if(ADDRESS_INPUT[0:0]==0) begin BHE <= 1; - data_bus_output_register <= {8'b0,DATA[7:0]}; + data_bus_output_register <= {8'b0,DATA_EX_WRITE[7:0]}; end else begin BHE <= 0; - data_bus_output_register <= {DATA[7:0],8'b0}; + data_bus_output_register <= {DATA_EX_WRITE[7:0],8'b0}; end write <= 0; biu_state <= `BIU_WRITE_RELEASE; @@ -235,7 +233,6 @@ always @(posedge clock) begin /*************** DATA READ ***************/ `define finished_read \ - DATA_DIR <= 0; \ if ( read_request == 0 ) begin \ biu_state <= `BIU_NEXT_ACTION;\ VALID_DATA <= 0;\ @@ -244,20 +241,20 @@ always @(posedge clock) begin `BIU_GET_ALIGNED_DATA:begin `ifdef DEBUG_DATA_READ_WRITES if(Wbit==1) - $display("Reading 16bit %04x from %04x",external_data_bus,DATA_ADDRESS); + $display("Reading 16bit %04x from %04x",external_data_bus_read,DATA_ADDRESS); else - $display("Reading 8bit %02x from %04x",external_data_bus[7:0],DATA_ADDRESS); + $display("Reading 8bit %02x from %04x",external_data_bus_read[7:0],DATA_ADDRESS); `endif - DATA_OUT <= (Wbit==1)? external_data_bus : {8'b0,external_data_bus[7:0]} ; + DATA_OUT <= (Wbit==1)? external_data_bus_read : {8'b0,external_data_bus_read[7:0]} ; read <=1; `finished_read end `BIU_GET_UNALIGNED_DATA:begin `ifdef DEBUG_DATA_READ_WRITES if(Wbit==0) - $display("Reading 8bit %02x from %04x",external_data_bus[15:8],DATA_ADDRESS); + $display("Reading 8bit %02x from %04x",external_data_bus_read[15:8],DATA_ADDRESS); `endif - DATA_OUT[7:0] <= external_data_bus[15:8]; + DATA_OUT[7:0] <= external_data_bus_read[15:8]; read <=1; if(Wbit==1) begin biu_state <= `BIU_GET_SECOND_BYTE; @@ -272,9 +269,9 @@ always @(posedge clock) begin end `BIU_GET_SECOND_BYTE1:begin `ifdef DEBUG_DATA_READ_WRITES - $display("Reading 16bit %02x from %04x",{external_data_bus[7:0],DATA_OUT[7:0]},DATA_ADDRESS-1);//read started a byte earlier + $display("Reading 16bit %02x from %04x",{external_data_bus_read[7:0],DATA_OUT[7:0]},DATA_ADDRESS-1);//read started a byte earlier `endif - DATA_OUT[15:8] <= external_data_bus[7:0]; + DATA_OUT[15:8] <= external_data_bus_read[7:0]; `finished_read read <=1; end @@ -293,7 +290,6 @@ always @(posedge clock) begin INSTRUCTION_ADDRESS <= 20'h0FFF0; INSTRUCTION_LOCATION <= 16'hFFF0; VALID_DATA <= 0; - DATA_DIR <= 0; sane<=1; end default: begin @@ -405,7 +401,6 @@ always @( posedge jump_req ) begin FIFO_start = FIFO_end ; /* verilator lint_on BLKSEQ */ jump_req_latch <= 1; - DATA_DIR <= 1; VALID_INSTRUCTION <= 0; end diff --git a/system/execute.v b/system/execute.v index 344e9dd..09a75e1 100644 --- a/system/execute.v +++ b/system/execute.v @@ -42,10 +42,10 @@ module execute_unit ( /* */ ,output reg biu_read_request, output reg biu_jump_req,output reg biu_write_request /*************** INPUT FROM BIU ****************/ - /* */ ,input BIU_VALID_DATA, input biu_data_direction + /* */ ,input BIU_VALID_DATA,input [15:0] BIU_EX_DATA_READ - /************ BIDIRECTIONAL WITH BIU ***********/ - /* */ ,inout [15:0] BIU_DATA + /**************** OUTPUT TO BIU ****************/ + /* */ ,output [15:0] BIU_EX_DATA_WRITE /***************** REGISTERS *****************/ /* */ ,input [15:0] reg_read_port1_data ,input [15:0] reg_read_port2_data, output reg [3:0] reg_read_port1_addr @@ -57,7 +57,7 @@ assign _ALU_O_ = ALU_O; reg [`EXEC_STATE_BITS-1:0] exec_state; reg [15:0] PARAM1,PARAM2; -assign BIU_DATA = biu_data_direction ? (memio_address_select ? reg_read_port1_data : ALU_O): 16'hz; +assign BIU_EX_DATA_WRITE = memio_address_select ? reg_read_port1_data : ALU_O; /*############ ALU / Execution units ################################################## */ @@ -210,7 +210,7 @@ always @(posedge clock) begin if ( BIU_VALID_DATA == 1 ) begin exec_state <= `EXEC_WRITE_ENTRY; - PARAM2 <= BIU_DATA; + PARAM2 <= BIU_EX_DATA_READ; biu_read_request <= 0; end else begin biu_read_request <= 1; diff --git a/system/memory.v b/system/memory.v index a2c7fb7..fa10293 100644 --- a/system/memory.v +++ b/system/memory.v @@ -19,7 +19,7 @@ /* This warning is because we don't use the full address bus. */ /* verilator lint_off UNUSEDSIGNAL */ -module doublemem(input [19:0] address,inout wire [15:0] data ,input rd,input wr,input BHE,input cs); +module doublemem(input [19:0] address,output [15:0] cpu_read_data ,input [15:0] cpu_write_data,input rd,input wr,input BHE,input cs); /* verilator lint_on UNUSEDSIGNAL */ reg [15:0] memory [0:32768]; @@ -38,16 +38,16 @@ initial begin `endif end -assign data[7:0] = !address[0:0] & !rd & !cs ? memory[address[16:1]][15:8] : 8'hz; +assign cpu_read_data[7:0] = !address[0:0] & !rd & !cs ? memory[address[16:1]][15:8] : 8'hz; -assign data[15:8] = !BHE & !rd & !cs ? memory[address[16:1]][7:0] : 8'hz; +assign cpu_read_data[15:8] = !BHE & !rd & !cs ? memory[address[16:1]][7:0] : 8'hz; always @(negedge wr) begin if( cs == 0 ) begin if(BHE==0) - memory[address[16:1]][7:0]<=data[15:8]; + memory[address[16:1]][7:0]<=cpu_write_data[15:8]; if(address[0]==0) - memory[address[16:1]][15:8]<=data[7:0]; + memory[address[16:1]][15:8]<=cpu_write_data[7:0]; end end diff --git a/system/processor.v b/system/processor.v index b786a35..7ef9e49 100644 --- a/system/processor.v +++ b/system/processor.v @@ -32,7 +32,7 @@ module processor ( /* MISC */ input clock, input reset, output wire HALT,output [`ERROR_BITS-1:0] ERROR - /* MEMORY / IO */ ,output [19:0] external_address_bus, inout [15:0] external_data_bus,output read, output write,output BHE,output IOMEM + /* MEMORY / IO */ ,output [19:0] external_address_bus, input [15:0] external_data_bus_read, output [15:0] external_data_bus_write,output read, output write,output BHE,output IOMEM `ifdef CALCULATE_IPC /* STATISTICS */ ,output wire new_instruction @@ -85,10 +85,10 @@ execute_unit execute_unit ( /* */ ,biu_read_request, biu_jump_req, biu_write_request /*************** INPUT FROM BIU ****************/ - /* */ ,BIU_VALID_DATA, BIU_DATA_DIR + /* */ ,BIU_VALID_DATA,BIU_EX_DATA_READ - /************ BIDIRECTIONAL WITH BIU ***********/ - /* */ ,BIU_DATA + /**************** OUTPUT TO BIU ****************/ + /* */ ,BIU_EX_DATA_WRITE /***************** REGISTERS *****************/ /* */ ,reg_read_port1_data, reg_read_port2_data, EXEC_reg_read_port1_addr @@ -99,11 +99,10 @@ execute_unit execute_unit ( /*############ Bus Interface Unit ############################################### */ wire [15:0] INSTRUCTION_LOCATION; -wire [15:0] BIU_DATA; +wire [15:0] BIU_EX_DATA_READ,BIU_EX_DATA_WRITE; wire [31:0] IF2DE_INSTRUCTION; wire BIU_VALID_DATA; wire VALID_INSTRUCTION; -wire BIU_DATA_DIR; BIU BIU( /***************** GENERAL *****************/ @@ -111,21 +110,21 @@ BIU BIU( /**************** OUTSIDE WORLD ****************/ /* */ ,external_address_bus - /* */ ,external_data_bus,read,write,BHE,IOMEM + /* */ ,external_data_bus_read,external_data_bus_write,read,write,BHE,IOMEM /**************** OUTPUT TO DE ****************/ /* */ ,IF2DE_INSTRUCTION,VALID_INSTRUCTION,INSTRUCTION_LOCATION - /* */ ,BIU_VALID_DATA,BIU_DATA_DIR + /* */ ,BIU_VALID_DATA /**************** INPUT FROM DE ****************/ ,Wbit,MEM_OR_IO,VALID_INSTRUCTION_ACK /**************** INPUT FROM EX ****************/ /* */ ,biu_jump_req,biu_write_request,biu_read_request - /* */ ,BIU_ADDRESS_INPUT + /* */ ,BIU_ADDRESS_INPUT,BIU_EX_DATA_WRITE - /************ BIDIRECTIONAL WITH EX ************/ - /* */ ,BIU_DATA + /***************** OUTPUT TO EX ****************/ + /* */ ,BIU_EX_DATA_READ `ifdef OTUPUT_JSON_STATISTICS /***************** STATISTICS *****************/ diff --git a/system/system.v b/system/system.v index 5d9ebc6..8971bb6 100644 --- a/system/system.v +++ b/system/system.v @@ -22,7 +22,7 @@ `include "config.v" -module system ( input clock,input reset, output [19:0]address_bus, inout [15:0]data_bus,output BHE, output rd, output wr, output IOMEM, output HALT, output [`ERROR_BITS-1:0] ERROR); +module system ( input clock,input reset, output [19:0]address_bus, input [15:0]data_bus_read, output [15:0]data_bus_write ,output BHE, output rd, output wr, output IOMEM, output HALT, output [`ERROR_BITS-1:0] ERROR); `ifdef CALCULATE_IPC wire new_instruction; @@ -33,9 +33,14 @@ wire unsigned [`L1_CACHE_SIZE-1:0] L1_SIZE_STAT; wire VALID_INSTRUCTION_STAT,jump_req; `endif +wire [15:0]data_bus_read_,data_bus_write_; + +assign data_bus_read_=data_bus_read; +assign data_bus_write=data_bus_write_; + processor p( /* MISC */ clock,reset,HALT,ERROR - /* MEMORY / IO */ ,address_bus,data_bus,rd,wr,BHE,IOMEM + /* MEMORY / IO */ ,address_bus,data_bus_read_,data_bus_write_,rd,wr,BHE,IOMEM `ifdef CALCULATE_IPC /* STATISTICS */ ,new_instruction `endif @@ -44,7 +49,7 @@ processor p( `endif ); -doublemem sysmem(address_bus,data_bus,rd,wr,BHE,IOMEM); +doublemem sysmem(address_bus,data_bus_read_,data_bus_write_,rd,wr,BHE,IOMEM); `ifdef OTUPUT_JSON_STATISTICS string stats_name,version,commit; @@ -99,7 +104,7 @@ end always @(negedge wr) begin if(IOMEM==1'b1 && address_bus[7:0]==8'hA5 ) - $write("%s" ,data_bus[15:8]); + $write("%s" ,data_bus_write[15:8]); end diff --git a/system/testbench.v b/system/testbench.v index 480398b..7dc4977 100644 --- a/system/testbench.v +++ b/system/testbench.v @@ -25,7 +25,7 @@ wire clock; reg reset; reg clk_enable; wire [19:0]address_bus; -wire [15:0]data_bus; +wire [15:0]data_bus_read,data_bus_write; wire rd,wr,HALT; wire [2:0] ERROR; wire IOMEM; @@ -33,7 +33,8 @@ wire IOMEM; system system( .clock(clock), .reset(reset), .address_bus(address_bus), - .data_bus(data_bus), + .data_bus_read(data_bus_read), + .data_bus_write(data_bus_write), .rd(rd), .wr(wr), .HALT(HALT),