From 36bf8f9c7a83abb12ab6c5e57f4bff8a904c3e7d Mon Sep 17 00:00:00 2001
From: "(Tim) Efthimis Kritikos" <efkf@firemail.cc>
Date: Thu, 2 Nov 2023 20:40:04 +0000
Subject: [PATCH] Added OrangeCrab board-specific code to connect the cpu to
 the outside world

---
 system/Makefile                               |  2 +-
 .../fpga_config/OrangeCrab_r0.2.1/fpga_top.v  | 55 +++++++++++++++++++
 .../OrangeCrab_r0.2.1/pin_constraint.pcf      | 10 ++--
 3 files changed, 61 insertions(+), 6 deletions(-)
 create mode 100644 system/fpga_config/OrangeCrab_r0.2.1/fpga_top.v

diff --git a/system/Makefile b/system/Makefile
index 28c6a5c..3a08d75 100644
--- a/system/Makefile
+++ b/system/Makefile
@@ -64,7 +64,7 @@ else
 $(error invalid ECP5 device ${ECP5_DEVICE})
 endif
 
-ECP5_TARGETS=synth_ecp5.json synth_ecp5_out.config synth_ecp5.bit synth_ecp5.dfu
+ECP5_TARGETS=synth_ecp5.json synth_ecp5_out.config synth_ecp5.bit synth_ecp5.dfu fpga_config/${FPGA_BOARD}/fpga_top.v
 ECP5_TARGETS+=abc.history # created from yosys
 
 synth_ecp5.json: ${SOURCES} ${TOP_LEVEL_SOURCE} ${INCLUDES} boot_code.txt
diff --git a/system/fpga_config/OrangeCrab_r0.2.1/fpga_top.v b/system/fpga_config/OrangeCrab_r0.2.1/fpga_top.v
new file mode 100644
index 0000000..52fdfb8
--- /dev/null
+++ b/system/fpga_config/OrangeCrab_r0.2.1/fpga_top.v
@@ -0,0 +1,55 @@
+/* top.v - Implements FPGA and Board specific circuitry
+
+   This file is part of the 9086 project.
+
+   Copyright (c) 2023 Efthymios Kritikos
+
+   This program is free software: you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation, either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
+
+`include "error_header.v"
+
+module fpga_top(
+	input clk48,
+
+	input user_button;
+	output reset_n;
+
+	output reg rgb_led0_r;
+	output reg rgb_led0_g;
+	output reg rgb_led0_b;
+);
+
+wire HALT,[`ERROR_BITS-1:0]ERROR;
+system system(
+	/*     MISC    */ clk48,user_button,HALT,ERROR
+	/* MEMORY / IO */ ,address_bus,data_bus,rd,wr,BHE,IOMEM
+)
+
+always @(HALT or ERROR or user_button) begin
+	if (HALT==0) begin
+		/* yellow */
+		rgb_led_r=0;
+		rgb_led_g=0;
+		rgb_led_b=1;
+	end else if (ERROR != `ERROR_BITS'b0) begin
+		/* red */
+		rgb_led_r=0;
+		rgb_led_g=1;
+		rgb_led_b=1;
+	end else begin
+		rgb_led_r=1;
+		rgb_led_g=0;
+		rgb_led_b=1;
+	end
+end
diff --git a/system/fpga_config/OrangeCrab_r0.2.1/pin_constraint.pcf b/system/fpga_config/OrangeCrab_r0.2.1/pin_constraint.pcf
index 65d3d3b..ce6be11 100644
--- a/system/fpga_config/OrangeCrab_r0.2.1/pin_constraint.pcf
+++ b/system/fpga_config/OrangeCrab_r0.2.1/pin_constraint.pcf
@@ -232,10 +232,10 @@ IOBUF PORT "gpio_a2" PULLMODE=DOWN;
 LOCATE COMP "gpio_a3" SITE "H4";
 IOBUF PORT "gpio_a3" IO_TYPE=LVCMOS33;
 IOBUF PORT "gpio_a3" PULLMODE=DOWN;
-LOCATE COMP "usr_btn" SITE "J17";
-IOBUF PORT "usr_btn" IO_TYPE=SSTL135_I;
-LOCATE COMP "rst_n" SITE "V17";
-IOBUF PORT "rst_n" IO_TYPE=LVCMOS33;
+LOCATE COMP "user_button" SITE "J17";
+IOBUF PORT "user_button" IO_TYPE=SSTL135_I;
+LOCATE COMP "reset_n" SITE "V17";
+IOBUF PORT "reset_n" IO_TYPE=LVCMOS33;
 LOCATE COMP "spiflash4x_cs_n" SITE "U17";
 IOBUF PORT "spiflash4x_cs_n" IO_TYPE=LVCMOS33;
 LOCATE COMP "spiflash4x_dq[0]" SITE "U18";
@@ -251,4 +251,4 @@ IOBUF PORT "usb_d_p" IO_TYPE=LVCMOS33;
 LOCATE COMP "usb_d_n" SITE "M2";
 IOBUF PORT "usb_d_n" IO_TYPE=LVCMOS33;
 LOCATE COMP "usb_pullup" SITE "N2";
-IOBUF PORT "usb_pullup" IO_TYPE=LVCMOS33;
\ No newline at end of file
+IOBUF PORT "usb_pullup" IO_TYPE=LVCMOS33;