From 2fcc521f12ac518a0e68eb575bbc953c9039ad63 Mon Sep 17 00:00:00 2001 From: "(Tim) Efthimis Kritikos" Date: Tue, 5 Dec 2023 02:49:28 +0000 Subject: [PATCH] Peripherals/Wishbone_memory: Rewrote the module to be more efficient, smaller and also support byte level addressing. It is correct enough now to run code out of! --- .../fpga_config/OrangeCrab_r0.2.1/fpga_top.v | 3 +- system/peripherals/Wishbone_memory_driver.v | 119 +++--------------- 2 files changed, 19 insertions(+), 103 deletions(-) diff --git a/system/fpga_config/OrangeCrab_r0.2.1/fpga_top.v b/system/fpga_config/OrangeCrab_r0.2.1/fpga_top.v index 13de6e8..1c2e1ed 100644 --- a/system/fpga_config/OrangeCrab_r0.2.1/fpga_top.v +++ b/system/fpga_config/OrangeCrab_r0.2.1/fpga_top.v @@ -269,12 +269,13 @@ Wishbone_memory_driver Wishbone_memory_driver( ////// CPU INTERFACE /////// .address(address_bus), + .BHE(BHE), .data_bus_in(data_bus_write), .data_bus_out(data_bus_read_DDR3), .wait_state(wait_state), .read_n(rd), .write_n(wr), - .chip_select_n(DDR3_ram_cs&&ddr3_init_done), + .chip_select_n(!(DDR3_ram_cs&&ddr3_init_done)), ////// WISHBONE INTERFACE ///// .wb_mem_ack(wb_mem_ack), diff --git a/system/peripherals/Wishbone_memory_driver.v b/system/peripherals/Wishbone_memory_driver.v index adb1f45..d1ebe20 100644 --- a/system/peripherals/Wishbone_memory_driver.v +++ b/system/peripherals/Wishbone_memory_driver.v @@ -24,14 +24,15 @@ module Wishbone_memory_driver ( input wire [19:0] address, input wire [15:0] data_bus_in, output reg [15:0] data_bus_out, - output reg wait_state, + output wire wait_state, input read_n, input write_n, input chip_select_n, + input BHE, input wire wb_mem_ack, output wire [24:0] wb_mem_adr, - output wire wb_mem_cyc, + output reg wb_mem_cyc, /* verilator lint_off UNUSEDSIGNAL */ // I don't yet use the upper word input wire [31:0] wb_mem_data_r, @@ -39,111 +40,25 @@ module Wishbone_memory_driver ( output wire [31:0] wb_mem_data_w, input wire wb_mem_err, output wire [3:0] wb_mem_sel, - output wire wb_mem_stb, + output reg wb_mem_stb, output wire wb_mem_we ); -reg WISHBONE_ACTIVE_CYCLE=1'b0; -/* verilator lint_off UNUSEDSIGNAL */ -wire WISHBONE_ERROR_IN; -/* verilator lint_on UNUSEDSIGNAL */ -reg [3:0]WISHBONE_SELECT=4'd0; -reg WISHBONE_VALID_TRANSFER=1'b0; -reg WISHBONE_WRITE=1'b1; -wire WISHBONE_ACK_IN; -reg [31:0]WISHBONE_DATA_READ=32'd0; -wire [15:0]WISHBONE_DATA_WRITE; - -assign WISHBONE_ACK_IN=wb_mem_ack; -assign wb_mem_adr={5'd0,address}; -assign WISHBONE_ERROR_IN=wb_mem_err; -assign wb_mem_sel=WISHBONE_SELECT; -assign wb_mem_stb=WISHBONE_VALID_TRANSFER; -assign wb_mem_cyc=WISHBONE_ACTIVE_CYCLE; -assign wb_mem_we=WISHBONE_WRITE; -assign WISHBONE_DATA_WRITE=wb_mem_data_r[15:0]; -assign wb_mem_data_w=WISHBONE_DATA_READ; - -wire CYCLE_END=(WISHBONE_ACK_IN==1'b1);//||WISHBONE_ERROR_IN==1'b1); - -reg [3:0] state; - -always @(*) begin - wait_state=0; - if(reset_n==1) begin - case(state) - 4'd0:begin - if( chip_select_n && ((!read_n)||(!write_n)) )begin - wait_state=1; - end else begin - wait_state=0; - end - end - 4'd1:begin - wait_state=1; - end - 4'd2:begin - wait_state=1; - end - 4'd3:begin - wait_state=1; - end - 4'd4:begin - wait_state=0; - end - default:begin - end - endcase - end else begin - wait_state=0; - end -end +assign wb_mem_adr={6'd0,address[19:1]}; +assign wb_mem_sel={2'b11,!BHE,!address[0]}; always @(posedge clock)begin - if(reset_n==0) - state<=0; - else begin - case(state) - 4'd0:begin - if( chip_select_n && ((!read_n)||(!write_n)) )begin - state<=4'd1; - end - end - 4'd1:begin - WISHBONE_ACTIVE_CYCLE<=1; - WISHBONE_VALID_TRANSFER<=1; - WISHBONE_SELECT<=4'hF; - WISHBONE_WRITE<=read_n; - if(read_n)begin - state<=4'd2; - WISHBONE_DATA_READ<={16'h0,data_bus_in}; - end else - state<=4'd3; - end - 4'd2:begin - if(CYCLE_END==1'b1)begin - state<=4'd4; - WISHBONE_ACTIVE_CYCLE<=0; - WISHBONE_VALID_TRANSFER<=0; - end - end - 4'd3:begin - if(CYCLE_END==1'b1)begin - data_bus_out<=WISHBONE_DATA_WRITE[15:0]; - state<=4'd4; - WISHBONE_ACTIVE_CYCLE<=0; - WISHBONE_VALID_TRANSFER<=0; - end - end - 4'd4:begin - if(read_n&&write_n) - state<=4'd0; - end - default:begin - state<=4'd0; - end - endcase - end + wb_mem_cyc<=( (!read_n||!write_n)^(wb_mem_ack) )&(!chip_select_n); + wb_mem_stb<=( (!read_n||!write_n)^(wb_mem_ack) )&(!chip_select_n); end +always @(posedge wb_mem_ack)begin + data_bus_out=wb_mem_data_r[15:0]; +end +assign wb_mem_data_w={16'd0,data_bus_in}; + +assign wait_state=( (!read_n||!write_n)^(wb_mem_ack) )&(!chip_select_n); + +assign wb_mem_we=read_n; + endmodule