From 1d9be44c5a756c22c134f0adba7f721b2e27731a Mon Sep 17 00:00:00 2001
From: "(Tim) Efthimis Kritikos" <efkf@firemail.cc>
Date: Mon, 22 Jan 2024 20:19:14 +0000
Subject: [PATCH] Build system: renamed upload to upload_bitstream to allow for
 an upload_firmware in the future

---
 Makefile                                       | 8 ++++----
 README.md                                      | 2 +-
 system/fpga_config/OrangeCrab_r0.2.1/config.mk | 2 +-
 3 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/Makefile b/Makefile
index a46a21a..b265d9e 100644
--- a/Makefile
+++ b/Makefile
@@ -54,9 +54,9 @@ mrproper: clean
 	${Q}make ${MAKEOPTS} PRINT_PATH_PREFIX=system/ -C system mrproper
 	${Q}make ${MAKEOPTS} PRINT_PATH_PREFIX=boot_code/ -C boot_code mrproper
 
-.PHONY: upload
-upload: boot_code/bios.stxt
-	${Q}make ${MAKEOPTS} PRINT_PATH_PREFIX=system/ -C system upload
+.PHONY: upload_bitstream
+upload_bitstream: boot_code/bios.stxt
+	${Q}make ${MAKEOPTS} PRINT_PATH_PREFIX=system/ -C system upload_bitstream
 
 .PHONY: fpga_sim
 fpga_sim: boot_code/bios.stxt
@@ -74,7 +74,7 @@ help:
 	@echo '  boot_code/[name].disas  - assemble and show the disassembly of the binary'
 	@echo ''
 	@echo 'Synthesis targets:'
-	@echo '  upload                  - Build a bitstream for the board selected in'
+	@echo '  upload_bitstream        - Build a bitstream for the board selected in'
 	@echo '                            common.mk and upload it if possible'
 	@echo '  fpga_sim                - Simulate the SoC that gets build for the configured'
 	@echo '                            fpga board'
diff --git a/README.md b/README.md
index d878166..1a3bd4f 100644
--- a/README.md
+++ b/README.md
@@ -29,7 +29,7 @@ This list shows the software needed and the versions used during development :
 After that you can run `make` on the top level directory and it should build everything and start the simulation
 
 ### Synthesis and bitstream creation for FPGAs
-You need to set FPGA\_BOARD in [./common.mk](./common.mk) to the name of a directory inside [./system/fpga\_config/](system/fpga_config/). You should also check inside your board directory for config.mk for further board-specific configuration options. Then you can run `make upload` in the top level directory and it should create the bitstream and upload it.
+You need to set FPGA\_BOARD in [./common.mk](./common.mk) to the name of a directory inside [./system/fpga\_config/](system/fpga_config/). You should also check inside your board directory for config.mk for further board-specific configuration options. Then you can run `make upload_bitstream` in the top level directory and it should create the bitstream and upload it.
 
 These are the currently supported FPGA boards:
 
diff --git a/system/fpga_config/OrangeCrab_r0.2.1/config.mk b/system/fpga_config/OrangeCrab_r0.2.1/config.mk
index bdee2fc..8906b13 100644
--- a/system/fpga_config/OrangeCrab_r0.2.1/config.mk
+++ b/system/fpga_config/OrangeCrab_r0.2.1/config.mk
@@ -26,7 +26,7 @@ FPGA_SOC_SIM_SOURCES=${FPGA_SOC_COMMON_SOURCES} fpga_config/OrangeCrab_r0.2.1/ve
 
 FPGA_BOOTCODE=../boot_code/bios.stxt
 
-upload: dfu_upload
+upload_bitstream: dfu_upload
 
 ${BUILD_FILES_PREFIX}bitstream_${BUILD_NAME}.bit:${BUILD_FILES_PREFIX}nextpnr-ecp5_${BUILD_NAME}.bit
 	${Q}cp "$^" "$@"