diff --git a/system/biu.v b/system/biu.v
index 7498680..6b4be68 100644
--- a/system/biu.v
+++ b/system/biu.v
@@ -117,7 +117,7 @@ always @(posedge clock) begin
 					BHE <= 0;
 					biu_state <= (ADDRESS_INPUT[0:0])?`BIU_GET_UNALIGNED_DATA:`BIU_GET_ALIGNED_DATA;
 				end else begin
-					if ( FIFO_SIZE!=4'hF ) begin
+					if ( FIFO_SIZE!={`L1_CACHE_SIZE{1'b1}} ) begin
 						func<=1;
 						biu_state <= `BIU_READ;
 						write <= 1;
@@ -133,29 +133,29 @@ always @(posedge clock) begin
 				if((Isit1==1) && (FIFO_SIZE!=0) && `EARLY_VALID_INSTRUCTION_)begin
 					VALID_INSTRUCTION <= 1;
 					INSTRUCTION[31:24] <= INPUT_FIFO[FIFO_start];
-				end else if((fifoIsize==2) && (FIFO_SIZE > 1) && `EARLY_VALID_INSTRUCTION_)begin
+				end else if((fifoIsize==2) && (FIFO_SIZE > `L1_CACHE_SIZE'd1) && `EARLY_VALID_INSTRUCTION_)begin
 					VALID_INSTRUCTION <= 1;
 					INSTRUCTION[31:24] <= INPUT_FIFO[FIFO_start];
-					INSTRUCTION[23:16] <= INPUT_FIFO[FIFO_start+4'd1];
-				end else if((fifoIsize==3) && (FIFO_SIZE > 2) && `EARLY_VALID_INSTRUCTION_)begin
+					INSTRUCTION[23:16] <= INPUT_FIFO[FIFO_start+`L1_CACHE_SIZE'd1];
+				end else if((fifoIsize==3) && (FIFO_SIZE > `L1_CACHE_SIZE'd2) && `EARLY_VALID_INSTRUCTION_)begin
 					VALID_INSTRUCTION <= 1;
 					INSTRUCTION[31:24] <= INPUT_FIFO[FIFO_start];
-					INSTRUCTION[23:16] <= INPUT_FIFO[FIFO_start+4'd1];
-					INSTRUCTION[15: 8] <= INPUT_FIFO[FIFO_start+4'd2];
-				end else if(FIFO_SIZE>3)begin
+					INSTRUCTION[23:16] <= INPUT_FIFO[FIFO_start+`L1_CACHE_SIZE'd1];
+					INSTRUCTION[15: 8] <= INPUT_FIFO[FIFO_start+`L1_CACHE_SIZE'd2];
+				end else if(FIFO_SIZE > `L1_CACHE_SIZE'd3)begin
 					VALID_INSTRUCTION <= 1;
 					INSTRUCTION[31:24] <= INPUT_FIFO[FIFO_start];
-					INSTRUCTION[23:16] <= INPUT_FIFO[FIFO_start+4'd1];
-					INSTRUCTION[15: 8] <= INPUT_FIFO[FIFO_start+4'd2];
-					INSTRUCTION[ 7: 0] <= INPUT_FIFO[FIFO_start+4'd3];
+					INSTRUCTION[23:16] <= INPUT_FIFO[FIFO_start+`L1_CACHE_SIZE'd1];
+					INSTRUCTION[15: 8] <= INPUT_FIFO[FIFO_start+`L1_CACHE_SIZE'd2];
+					INSTRUCTION[ 7: 0] <= INPUT_FIFO[FIFO_start+`L1_CACHE_SIZE'd3];
 				end
 				`else
-				if(FIFO_SIZE>3)begin
+				if(FIFO_SIZE>`L1_CACHE_SIZE'd3)begin
 					VALID_INSTRUCTION <= 1;
 					INSTRUCTION[31:24] <= INPUT_FIFO[FIFO_start];
-					INSTRUCTION[23:16] <= INPUT_FIFO[FIFO_start+4'd1];
-					INSTRUCTION[15: 8] <= INPUT_FIFO[FIFO_start+4'd2];
-					INSTRUCTION[ 7: 0] <= INPUT_FIFO[FIFO_start+4'd3];
+					INSTRUCTION[23:16] <= INPUT_FIFO[FIFO_start+`L1_CACHE_SIZE'd1];
+					INSTRUCTION[15: 8] <= INPUT_FIFO[FIFO_start+`L1_CACHE_SIZE'd2];
+					INSTRUCTION[ 7: 0] <= INPUT_FIFO[FIFO_start+`L1_CACHE_SIZE'd3];
 				end
 				`endif
 
@@ -164,18 +164,18 @@ always @(posedge clock) begin
 
 			/*************** INSTRUCTION FIFO READ ***************/
 			`BIU_READ: begin
-				if(INSTRUCTION_ADDRESS[0:0]==0 && FIFO_SIZE<4'hD)begin
+				if(INSTRUCTION_ADDRESS[0:0]==0 && FIFO_SIZE<{{(`L1_CACHE_SIZE-1){1'b1}},1'b0})begin
 					INPUT_FIFO[FIFO_end] <= external_data_bus[7:0];
-					INPUT_FIFO[FIFO_end+4'd1] <= external_data_bus[15:8];
-					FIFO_end <= FIFO_end+4'd2;
+					INPUT_FIFO[FIFO_end+`L1_CACHE_SIZE'd1] <= external_data_bus[15:8];
+					FIFO_end <= FIFO_end+`L1_CACHE_SIZE'd2;
 					INSTRUCTION_ADDRESS <= INSTRUCTION_ADDRESS+20'd2;
 				end else if(INSTRUCTION_ADDRESS[0:0]==0)begin
 					INPUT_FIFO[FIFO_end] <= external_data_bus[7:0];
-					FIFO_end <= FIFO_end+4'd1;
+					FIFO_end <= FIFO_end+`L1_CACHE_SIZE'd1;
 					INSTRUCTION_ADDRESS <= INSTRUCTION_ADDRESS+20'd1;
 				end else begin
 					INPUT_FIFO[FIFO_end] <= external_data_bus[15:8];
-					FIFO_end <= FIFO_end+4'd1;
+					FIFO_end <= FIFO_end+`L1_CACHE_SIZE'd1;
 					INSTRUCTION_ADDRESS <= INSTRUCTION_ADDRESS+20'd1;
 				end
 				biu_state <= `BIU_NEXT_ACTION;
@@ -280,9 +280,9 @@ always @(posedge clock) begin
 			/*************** HOUSE KEEPING ***************/
 			`BIU_RESET: begin
 				/* verilator lint_off BLKSEQ */
-				FIFO_start = 4'b0;
+				FIFO_start = `L1_CACHE_SIZE'b0;
 				/* verilator lint_on BLKSEQ */
-				FIFO_end <= 4'b0;
+				FIFO_end <= `L1_CACHE_SIZE'b0;
 				biu_state <= `BIU_NEXT_ACTION;
 				INSTRUCTION_ADDRESS <= 20'h0FFF0;
 				INSTRUCTION_LOCATION <= 16'hFFF0;
@@ -303,36 +303,39 @@ InstrSize InstrSize({INSTRUCTION[31:24],INSTRUCTION[21:19]},Isize);
 `ifdef INCLUDE_EARLY_CALC_CIRUIT
 wire [2:0] fifoIsize;
 wire Isit1;
-InstrSize fifoInstrSize({INPUT_FIFO[FIFO_start][7:0],INPUT_FIFO[FIFO_start+4'd1][5:3]},fifoIsize);
+InstrSize fifoInstrSize({INPUT_FIFO[FIFO_start][7:0],INPUT_FIFO[FIFO_start+`L1_CACHE_SIZE'd1][5:3]},fifoIsize);
 Is1 Is1(INPUT_FIFO[FIFO_start][7:0],Isit1);
 `endif
 
 `ifdef DOUBLE_INSTRUCTION_LOAD
 wire [2:0] fifoIsize2;
-InstrSize fifoInstrSize2({INPUT_FIFO[FIFO_start+fifoIsize][7:0],INPUT_FIFO[FIFO_start+fifoIsize+4'd1][5:3]},fifoIsize2);
+InstrSize fifoInstrSize2(
+	{ INPUT_FIFO[FIFO_start+{{`L1_CACHE_SIZE-3{1'b0}},fifoIsize}][7:0], INPUT_FIFO[FIFO_start+{{`L1_CACHE_SIZE-3{1'b0}},fifoIsize}+`L1_CACHE_SIZE'd1][5:3]}
+	,fifoIsize2
+	);
 `endif
 
 always @( valid_instruction_ack ) begin
 	/* verilator lint_off BLKSEQ */
-	FIFO_start = FIFO_start + {1'b0,Isize};
-	INSTRUCTION_LOCATION <= INSTRUCTION_LOCATION + {12'b0,Isize};;
+	FIFO_start = FIFO_start + {{`L1_CACHE_SIZE-3{1'b0}},Isize};
+	INSTRUCTION_LOCATION <= INSTRUCTION_LOCATION + {13'd0,Isize};
 	`ifdef DOUBLE_INSTRUCTION_LOAD
-	if(FIFO_SIZE>4'd3+Isize)begin
-		if((fifoIsize2==2) && (FIFO_SIZE > 1+fifoIsize) && `EARLY_VALID_INSTRUCTION_)begin
+	if(FIFO_SIZE>`L1_CACHE_SIZE'd3+{{`L1_CACHE_SIZE-3{1'b0}},Isize})begin
+		if((fifoIsize2==2) && (FIFO_SIZE > `L1_CACHE_SIZE'd1+{{`L1_CACHE_SIZE-3{1'b0}},fifoIsize}) && `EARLY_VALID_INSTRUCTION_)begin
 			VALID_INSTRUCTION <= 1;
 			INSTRUCTION[31:24] <= INPUT_FIFO[FIFO_start];
-			INSTRUCTION[23:16] <= INPUT_FIFO[FIFO_start+4'd1];
-		end else if((fifoIsize2==3) && (FIFO_SIZE > 2+fifoIsize) && `EARLY_VALID_INSTRUCTION_)begin
+			INSTRUCTION[23:16] <= INPUT_FIFO[FIFO_start+`L1_CACHE_SIZE'd1];
+		end else if((fifoIsize2==3) && (FIFO_SIZE > `L1_CACHE_SIZE'd2+{{`L1_CACHE_SIZE-3{1'b0}},fifoIsize}) && `EARLY_VALID_INSTRUCTION_)begin
 			VALID_INSTRUCTION <= 1;
 			INSTRUCTION[31:24] <= INPUT_FIFO[FIFO_start];
-			INSTRUCTION[23:16] <= INPUT_FIFO[FIFO_start+4'd1];
-			INSTRUCTION[15: 8] <= INPUT_FIFO[FIFO_start+4'd2];
-		end else if(FIFO_SIZE>3+fifoIsize)begin
+			INSTRUCTION[23:16] <= INPUT_FIFO[FIFO_start+`L1_CACHE_SIZE'd1];
+			INSTRUCTION[15: 8] <= INPUT_FIFO[FIFO_start+`L1_CACHE_SIZE'd2];
+		end else if(FIFO_SIZE>`L1_CACHE_SIZE'd3+{{`L1_CACHE_SIZE-3{1'b0}},fifoIsize})begin
 			VALID_INSTRUCTION <= 1;
 			INSTRUCTION[31:24] <= INPUT_FIFO[FIFO_start];
-			INSTRUCTION[23:16] <= INPUT_FIFO[FIFO_start+4'd1];
-			INSTRUCTION[15: 8] <= INPUT_FIFO[FIFO_start+4'd2];
-			INSTRUCTION[ 7: 0] <= INPUT_FIFO[FIFO_start+4'd3];
+			INSTRUCTION[23:16] <= INPUT_FIFO[FIFO_start+`L1_CACHE_SIZE'd1];
+			INSTRUCTION[15: 8] <= INPUT_FIFO[FIFO_start+`L1_CACHE_SIZE'd2];
+			INSTRUCTION[ 7: 0] <= INPUT_FIFO[FIFO_start+`L1_CACHE_SIZE'd3];
 		end else
 			VALID_INSTRUCTION <= 0;
 	end else begin
diff --git a/system/config.v b/system/config.v
index cb31eea..e1d2a5a 100644
--- a/system/config.v
+++ b/system/config.v
@@ -42,7 +42,7 @@
  *   4 : 16 Bytes
  *   5 : 32 Bytes
  *   . :  ... */
-`define L1_CACHE_SIZE 4 // Don't change it! some parts of code still assume it to be 4
+`define L1_CACHE_SIZE 4