<img width="186" height="70" style=" margin: 10px 0px 10px 10px;" alt="9086 logo" src="readme_files/9086_design1.svg">


A CPU that aims to be binary compatible with the 8086 ISA, focused on optimisation and flexibility.

### Progress

* [ ] 8086
  * [X] Executing code
  * [X] Is Turing complete
  * [ ] Can boot up MS-DOS / FreeDOS
  * [ ] Is completely binary compatible
  * [X] Is pipelined
  * [ ] Is Out of Order
  * [ ] Is superscalar
  * [X] Has been successfully synthesized
  * [ ] Has a comprehensive testing framework

### Simulating it
Both Verilator and Icarus Verilog can be used for simulation. You can select which one you want with the SIM variable on [./common.mk](./common.mk).
This list shows the software needed and the versions used during development :

* Icarus Verilog : version 12.0  OR **(preferred)** Verilator : 5.028
* bin86 : 0.16.21
* GNU Make : 4.4.1
* xxd : 2025-08-08
* POSIX coreutils : GNU coreutils 9.8

After that you can run `make` on the top level directory and it should build everything and start the simulation

### Synthesis and bitstream creation for FPGAs
You need to set FPGA\_BOARD in [./common.mk](./common.mk) to the name of a directory inside [./system/fpga\_config/](system/fpga_config/). You should also check inside your board directory for config.mk for further board-specific configuration options like the model of I2C boot rom (if any). Then you can run `make upload_bitstream` in the top level directory and it should create the bitstream and upload it to the fpga. Depending on the board you might need to run `make upload_bootrom` to upload the boot code to an I2C eeprom.

These are the currently supported FPGA boards:

* [OrangeCrab r0.2.1](system/fpga_config/OrangeCrab_r0.2.1/README.md) ( last tested with commit fde181aa66 )

This list shows the software needed and the versions used during development :

* yosys : 0.37
* bin86 : 0.16.21
* GNU Make : 4.4.1
* xxd : 2023-10-25
* POSIX coreutils : GNU coreutils 9.4

Additionally, for ECP5 FPGAs:

* prjtrellis : 1.4 ( database commit 015e0330630d7c238c0e4f2cdd9c8157eb78c54a )
* nextpnr : 0.9

Additionally, for FPGAs using the [foboot](https://github.com/im-tomu/foboot) bootloader

* dfu-util : 0.11

Additionally, for boards that require an I2C eeprom to boot from

* minipro : 0.6 - ( git commit a227bce77d1b592785558e0af58ae2b0b97d4a23 )

Additionally, if you need a DRAM/DDR controller, the project supports litedram but all the dependencies
needed to build it are downloaded automatically by the appropriate script.

### High level design overview

<img width="700" style=" margin: 10px 0px 10px 10px;" alt="9086 logo" src="readme_files/9086_overview.svg">

### License and Copyright
All parts of this project and files in this repository are licensed under the GNU General Public License version 3 or later

Efthymios Kritikos is the copyright owner for all files except the following:

|    File                                                    | Copyright owner | Original license |
| :--------------------------------------------------------: | :-------------: | :--------------: |
| system/fpga\_config/OrangeCrab\_r0.2.1/pin\_constraint.pcf |   Greg Davill   |       MIT        |

### Version names
The version name consist of three numbers:

1. The CPU that this version aims to be compatible with
1. The specific milestone
1. Patch level

For example v1.3.2 aims to support 80186 code, is on the fourth milestone and has 2 bug fixes since the milestone was reached.
A "-dev" suffix denotes that the code is in the process to become that version, so in-between that and the previous.
